1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (36/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
 Jitter Notes
NOTE 1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one
Mode Register Set command is registered at Tm, another Mode Register Set command may be
registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
NOTE 2. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#,
ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec
values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup
and hold are relative to the clock signal crossing that latches the command/address. That is, these
parameters should be met whether clock jitter is present or not.
NOTE 3. These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)#) crossing to its
respective clock signal (CK, CK#) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is,
these parameters should be met whether clock jitter is present or not.
NOTE 4. These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition
edge to its respective data strobe signal (DQS(L/U), DQS(L/U)#) crossing.
NOTE 5. For these parameters, the DDR3L SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] /
tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
NOTE 6. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM
input clock.)
NOTE 7. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
Table 21. Input clock jitter spec parameter
Parameter
Symbol
-12
Unit
Min.
Max.
Clock period jitter
t_JIT (per)
-70
70
ps
Clock period jitter during DLL locking period
t_JIT (per,lck) -60
60
ps
Cycle to cycle clock period jitter
t_JIT (cc)
140
ps
Cycle to cycle clock period jitter during DLL locking period t_JIT (cc,lck)
120
ps
Cumulative error across 2 cycles
t_ERR (2per)
-103
103 ps
Cumulative error across 3 cycles
t_ERR (3per)
-122
122 ps
Cumulative error across 4 cycles
t_ERR (4per)
-136
136 ps
Cumulative error across 5 cycles
t_ERR (5per)
-147
147 ps
Cumulative error across 6 cycles
t_ERR (6per)
-155
155 ps
Cumulative error across 7 cycles
t_ERR (7per)
-163
163 ps
Cumulative error across 8 cycles
t_ERR (8per)
-169
169 ps
Cumulative error across 9 cycles
t_ERR (9per)
-175
175 ps
Cumulative error across 10 cycles
t_ERR (10per) -180
180 ps
Cumulative error across 11 cycles
t_ERR (11per) -184
184 ps
Cumulative error across 12 cycles
Cumulative error across n cycles, n=13...50, inclusive
t_ERR (12per) -188
188 ps
t_ERR (nper)
t_ERR (nper)min = (1+0.68ln(n)) * t_JIT (per)min
t_ERR (nper)max = (1+0.68ln(n)) * t_JIT (per)max
ps
Confidential
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Rev. 2.0
Aug. /2014