1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (38/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
Figure 12. Change Frequency during Precharge Power-down
PREVIOUS CLOCK FREQUENCY
NEW CLOCK FREQUENCY
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
CK#
CK
CKE
tCH tCL
tCK
tIH
tIS
tCKSRE
tCPDED
tCKE
tCHb tCLb
tCKSRX
tCKb
tIH
tIS
tCHb tCLb
tCKb
COMMAND
NOP
NOP
NOP
NOP
NOP
MRS
ADDRESS
ODT
tAOFPD / tAOF
DLL
RESET
tXP
DQS#
DQS
DQ
High-Z
High-z
Te0
Te1
tCHb tCLb
tCKb
NOP
tIH
VALID
VALID
tIS
DM
NOTES
Enter PRECHARGE
Power-Down Mode
Frequency Change
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
Exit PRECHARGE
Power-Down Mode
tDLLK
Indicates a break
in time scale
Don't Care
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1;refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 13. If the RTT_NOM feature was disabled in the mode
register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
Confidential
38
Rev. 2.0
Aug. /2014