1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (16/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
- Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP
to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (ns)
by tCK (ns) and rounding up to the next integer: WR min [cycles] = Roundup (tWR [ns]/tCK [ns]). The WR must
be programmed to be equal or larger than tWR (min).
- Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or
‘slow-exit’, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit
requires tXPDLL to be met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is
maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to
the next valid command.
 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance,
additive latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS#,
RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according
to the following figure.
Table 7. Extended Mode Register EMR (1) Bitmap
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0^*1
0
1
Qoff 0^*1
0^*1
Rtt_No
m
0^*1
Level
Rtt_No
m
D.I.C
AL
Rtt_No
m
D.I.C
DLL
Mode Register (1)
BA1 BA0 MRS mode
00
MR0
01
MR1
10
MR2
11
MR3
A4 A3
00
01
10
11
Additive Latency
0 (AL disabled)
CL – 1
CL – 2
Reserved
A0 DLL Enable
0
Enable
1
Disable
A12
Qoff ^*2
0
Output buffer enabled
A9 A6 A2
Rtt_Nom ^*3
1
Output buffer disabled
0 0 0 Rtt_Nom disabled
001
RZQ/4
A7
Write leveling enable
010
RZQ/2
0
1
Note: RZQ = 240 Ω
Disabled
Enabled
011
100
101
RZQ/6
RZQ/12 ^*4
RZQ/8 ^*4
A5
A1 Output Driver Impedance Control
110
Reserved
0
0
0
1
RZQ/6
RZQ/7
111
Reserved
Note: RZQ = 240 Ω
1
0
Reserved
1
1
Reserved
Note 1: BA2 and A8, A10 ~ A11 are RFU and must be programmed to 0 during MRS.
Note 2: Outputs disabled - DQs, DQSs, DQS#s.
Note 3: In Write leveling Mode (MR1 [bit7] = 1) with MR1 [bit12] =1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1 [bit7] = 1) with MR1 [bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are
allowed.
Note 4: If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Confidential
16
Rev. 2.0
Aug. /2014