1GB-DDR3L-AS4C64M16D3L Datasheet, PDF (27/90 Pages) Alliance Semiconductor Corporation – JEDEC Standard Compliant

1Gb DDR3L – AS4C64M16D3L
t_WTR
t_WR
t_MRD
t_MOD
t_CCD
t_DAL(min)
t_MPRR
t_RRD
t_FAW
t_IS(base)
t_IH(base)
t_IPW
t_ZQinit
t_ZQoper
t_ZQCS
t_XPR
t_XS
t_XSDLL
t_CKESR
t_CKSRE
t_CKSRX
t_XP
t_XPDLL
t_CKE
t_CPDED
t_PD
t_ACTPDEN
t_PRPDEN
t_RDPDEN
t_WRPDEN
t_WRAPDEN
t_WRPDEN
Delay from start of internal write
transaction to internal read command
max
(4t_CK,
-
7.5ns)
WRITE recovery time
15
-
Mode Register Set command cycle time
4
-
Mode Register Set command update delay
max
12t_CK,
-
15ns)
CAS# to CAS# command delay
4
-
Auto precharge write recovery + prechargetime
Multi-Purpose Register Recovery Time
WR + t_RP
1
-
ACTIVE to ACTIVE command period
max
(4t_CK,
-
7.5ns)
Four activate window
40
-
Command and Address setup time to CK,
AC160 60
-
CK# referenced to Vih(ac) / Vil(ac) levels
AC135 185
-
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
DC90
130
-
Control and Address Input pulse width for each input
560
-
Power-up and RESET calibration time
512
-
Normal operation Full calibration time
256
-
Normal operation Short calibration time
64
-
Exit Reset from CKE HIGH to a valid command
max(5tCK,
tRFC(min) +
-
10ns)
Exit Self Refresh to commands not
requiring a locked DLL
max(5tCK,
tRFC(min) +
-
10ns)
Exit Self Refresh to commands requiring a
locked DLL
tDLLK(min)
-
Minimum CKE low width for Self Refresh
entry to exit timing
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry (SRE) max(5t_CK,
or Power-Down Entry (PDE)
10 ns)
-
Valid Clock Requirement before Self Refresh Exit (SRX) max(5t_CK,
or Power-Down Exit (PDX) or Reset Exit
10 ns)
-
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
max(3tCK,
6 ns)
-
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
max(10tCK,
24 ns)
-
CKE minimum pulse width
max(3tCK,
5 ns)
-
Command pass disable delay
2
-
Power Down Entry to Exit Timing
Timing of ACT command to Power Down
entry
Timing of PRE or PREA command to
Power Down entry
Timing of RD/RDA command to Power
Down entry
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
tCKE(min)
1
9 * tREFI
-
1
-
RL + 4 + 1
-
WL + 4 +
(tWR / tCK)
-
WL + 4 +
WR + 1
-
WL + 2 +
(tWR / tCK)
-
tCK
18
ns
18
tCK
tCK
tCK
tCK
tCK
22
tCK
ns
ps
16
ps 16,27
ps
16
ps
28
tCK
tCK
tCK
23
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
2
tCK
tCK
15
tCK
20
tCK
20
tCK
tCK
9
tCK
10
tCK
9
Confidential
27
Rev. 2.0
Aug. /2014