MDS212 Datasheet, PDF (98/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
h0c8
h108
h148
h188
h1c8
h208
h248
h288
h2c8
ECR2_p3
ECR2_p4
ECR2_p5
ECR2_p6
ECR2_p7
ECR2_p8
ECR2_p9
ECR2_p10
ECR2_p11
31
2 ₁‘0
Mask
Bit [0]
WAS
If set, the status counter wrap around signal is masked.
Bit [1]
Link_Change
If set, the Link_Up and Link_Down Interrupts are masked.
Bit [31:2]
Reserved
• Link Change interrupts are automatically disabled whenever both MAC Transmitter & Receiver are in Reset
state – i.e. both XR & RR bits are set.
18.2.12.4 ECR3 - MAC Port Interrupt Status Register
• Access:
• Address:
Non-Zero-Wait-State,
h0x3*4
h00c
h04c
h08c
h0cc
h10c
h14c
h18c
h1cc
h20c
h24c
h28c
h2cc
Direct Access,
x: port number
ECR3_p0
ECR3_p1
ECR3_p2
ECR3_p3
ECR3_p4
ECR3_p5
ECR3_p6
ECR3_p7
ECR3_p8
ECR3_p9
ECR3_p10
ECR3_p11
Read only
31
Bit [0]
Bit [1]
Bit [2]
Bit [31:3]
WAS
Link_Change
LK_UP
Reserved
3
2₁ 0
Status
Wrapped around signal.
This bit is set when the MAC determines that the status of
physical link has been changed
0=Link Down, 1=Link UP
This bit is reset whenever the PHY has identified the lost of
physical link integrity.
98
Zarlink Semiconductor Inc.