MDS212 Datasheet, PDF (82/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Bit [1]
Bit [2]
Bit [3]
Bit [31:4]
Free Mail Box is not ready for CPU to put entry into
1= Not Ready
0=Ready
CPU gets Mail from HISC
1= Ready
0=Not Ready
Free Mail Box has entry for CPU to get
1=Ready
0=Not Ready
Reserved
18.2.7.2 AMBX - Mail Box Access Port
• Access:
Zero-Wait-State,
Direct Access,
• Address:
h684
• In write mode, CPU sends Mail to HISC
• In Read mode, CPU receives Mail from HISC
31 30
21 20
Entry Handle
Write/Read
01 0
0 00
Bit [20:0]
Bit [29:21]
Bit [30]
Bit [31]
Reserved
Entry handle, the bit [2:0] always 2’b000
Link List is Empty. (Read only)
Link List is Ready. (Same as bit [0] of LKS register)
(Read only)
18.2.7.3 AFML - Free Mail Box List Access Port
• Access:
• Address:
Zero-Wait-State,
h688
Direct Access,
31 30
20
Entry Handle
Write/Read
0¹
0 00
Bit [20:0]
Bit [29:21]
Bit [30]
Bit [31]
Reserved
Entry handle, the bit [2:0] always 2’b000
Link List is Empty. (Read only)
Link List is Ready.
(Same as bit [1] of LKS register) (Read only)
18.2.8 Access Control Function
18.2.8.1 AVTC - VLAN Type Code Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h648
Write/Read
31
24 23
16 15
P7 P6 P5 P4 P3 P2 P1 P0
87
0
VLAN Type Code
82
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