MDS212 Datasheet, PDF (29/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

FDB block
must start from 0
MDS212
63
0
0
FDB
Frame Data Buffers
(1.5KB x # of frame buffers)
Data Sheet
Programmable Size
Transmission queues
(4x12=48 queues)
(each entry = 1DW)
(# entry of Queue = 128 to 1K)
CPU/HISC Mailing List
(# entry = 128 to 1K)
(each mail entry = 32 bytes to 64 bytes)
VLAN Table
(4k entry, 8B/entry)
VLAN MAC Table
(2k entry)
(each entry = 256, 128 or 64 bit)
Byte Byte Byte Byte Byte Byte Byte Byte
7
6
5
4
3
2
1
0
Programmable Size
32KB
16, 32 or 64KB
MAX
1/2MB, 1MB or 2MB
Figure 4 - Memory Map of Managed System
5.2.1.2 Transmission Queues
The Transmission Queues controls the scheduling of the transmission ports, where each of these ports can support
up to 4 priorities. There are up to 48 individual Transmission Queues, which represents 4 priorities for each of the
12 ports of the MDS212. The number of priorities is programmable. Thus, the MDS212 may be configured for 12,
24, 36, or 48 Transmission Queues and may support 1, 2, 3, or 4 priority levels, respectively. The size per
Transmission Queue is 128, 256, 512, or 1024 entries and may be setup during the initialization phase.
The Search Engine maintains the contents of each queue, where each queue consists of transmission priorities.
Each double word (4-bytes) entry contains a FDB handle, which points to the corresponding frame in the buffer.
5.2.1.3 Mailing List
The Mailing List provides a communication channel between the HISC and CPU in managed mode. The size of a
mail entry varies, ranging from 32 to 64 bytes, which is determined by the initialization setup. When the CPU or the
HISC writes mail, the CPU/HISC can obtain a free mail by the register AFML that contains the addresses of free
mail. Conversely, when the CPU or HISC reads its mail, the CPU/HISC accesses the mail by the register AMBX
that contains the address of a CPU/HISC mail. All of the mail registers are maintained by the hardware.
5.2.1.4 VLAN Table
The VLAN Table associates the ports to their respective VLANs, using the VLAN ID. The table contains 4K VLAN
entries, where each entry contains 8 bytes of information. The size of the VLAN Table is 32KB (4Kx8B). The base
address of the VLAN Table is specified by the VIDB in the VTBP bit [5:0].
Note: The VLAN Table must be located at the 32K boundary.
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