MDS212 Datasheet, PDF (97/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Physical Layer Control Bits
Used to enable protocol filtering on a port by port basis. There
is only one Protocol Filtering Register (PFR), but it can be used
on any combination of ports.
0= disable ingress filter 1= enable ingress filter
Bit [7]
Bit [8]
Bit [9]
Bit [10]
Bit [11]
Bit [12]
Bit [13]
10M
Reserved
Full_Duplex
FDX_Polarity
Int_Lpback
Ext_Lpback
FC_Enable
10M or 100M; 1=10Mbps 0=100Mbps
Enables full duplex mode Default =0 – Half Duplex
Selects the output polarity of Full_Duplex control signal
0 = Low true (Default) 1 = High true
Setting this bit cause internal connect
TXCLK, TXD, TXD[0:3] to RXCLK, RXD, RXD[0:3]
Default =0 – Disable
Setting this bit indicate an external loop-back connection of
TXCLK, TXD[0:3] to RXCLK, RXD[0:3] are required)
Default =0 -- Disable
Flow Control Enable Default =0 – Disable
When enabled:
• In Half Duplex mode, the MAC Transmitter applies backpressure for flow control.
• In Full Duplex mode, the MAC Transmitter sends Flow-Control frames when necessary. The MAC Receiver
interprets and processes incoming Flow Control frames. The MAC Receiver marks all Flow Control Frames.
Receive DMA discards the received Flow Control Frame and send status reports to the Switch Manager for
statistic collection.
When Disabled:
• The MAC Transmitter asserts flow control neither by sending Flow Control frames nor by jamming collision.
• The MAC Receiver still interprets and processes the Flow-Control frames. The MAC Receiver marks all
Flow Control frames. Receive DMA discards the received Flow Control frames and send a status report to
the Switch Manager for statistic collection.
Bit [14]
Link_Polarity
Selects the input polarity of Link Status signal
0 = Low true (Default) 1 = High true
Bit [15]
Tx_Enable
Enables MAC Transmitter for transmission
Default =0 – Disable
Bit [16]
Reserved
Bit [23:17]
IFG
Inter-frame Gap (Default=7’d24)
Use to adjust the inter-frame gap. (Unit =transmit Clock.) The
default is 7'd24, stands for 24 transmit clock (each clock
transmit 4 bits).
Bit [31:24]
Reserved
18.2.12.3 ECR2 - MAC Port Interrupt Mask Register
• Access:
• Address:
Non-Zero-Wait-State,
h0x2*4
h008
h048
h088
Direct Access,
x: port number
ECR2_p0
ECR2_p1
ECR2_p2
Write/Read
97
Zarlink Semiconductor Inc.