MDS212 Datasheet, PDF (93/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Bit[15:11]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit [30:16]
Bit [31]
Table bit map
MCID
VMAP
BMCT
FCB
QCNT
Reserve
C_RDY
Bit maps of five tables.
MCID=1 Use MC ID l Table
VMAP=1 Use VLAN port mapping Table (VMAP)
BMCT=1 Use Buffer Manager Control Table (BM control)
FCB=1 Use FCB Table
QCNT=1 Use Transmission Queue control Table (QM control)
Command Ready
0=Not Ready 1=Ready
18.2.11.9 CPUIRDAT - CPU Internal RAM Data Register
• The 3 data registers are used when CPU reads or writes the content of the specified entry table.
• CPUIRDAT0
CPU Internal RAM Data register for Data[31:0]
• Address:
h588
• CPUIRDAT1
CPU Internal RAM Data register for Data[63:32]
• Address:
h58C
• CPUIRDAT2
CPU Internal RAM Data register for Data[95:64]
• Address:
h590
• Access:
Non-Zero-Wait-State, Direct Access,
Write/Read
31
0
CPIRDAT0
Data[31:0]
CPIRDAT1
Data[63:32]
CPIRDAT2
Data[95:64]
The content is dependent on the type of table, as described below:
Type = MC ID (6bits)
31
CPIRDAT0
Bit [5:0]
Bit [31:6]
MCID
Reserved
13 12
65
0
MCID[5:0]
multicast ID FIFO data output
(Note that up to 16 for this version.)
Type = VMAP Table (27 bits)
31
CPIRDAT0
Bit [11:0]
Bit [12]
Bit [24:13]
27 26 25 24
13 12 11
0
RE
VLAN Tag Enable [12:0]
VLAN Port Enable [12:0]
VLAN Port Enable [12:0]one bit for each Ethernet MAC Port
Identify the ports associated with each VLAN
0 = disable 1 = enable
Reserved
VLAN Tag Enable [12:0]one bit for each Ethernet MAC Port
0 = disable 1 = enable
93
Zarlink Semiconductor Inc.