MDS212 Datasheet, PDF (85/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
18.2.10 Flow Control Management
18.2.10.1 AFCRIA - Flow Control RAM Input Address
Access:
Address:
Non-Zero-Wait-State, Direct Access, Write only
h65C
31
32
0
address
Bit [2:0]
3-bit address for the RAM in MAC storing flow control frame
Data Sheet
Usage: Flow Control Frame consists of 64 Bytes. Using AFCRIA and AFCRID0-1, the CPU loads 8 bytes each
time. The CPU specifies the address in AFCRIA and writes the content of 4 bytes in AFCRID0 and 4 Bytes in
AFCRID1. Then repeats the above procedure 8 times to load a whole flow control frame into the Chip.
18.2.10.2 AFCRID0 - Flow Control RAM Input Data 0
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h660
Write only
31
24 23
16 15
87
0
Content of Input Flow Control Frame[31:0]
Bit [31:0]
Content of flow control frame [31:0],
Flow Control Frame has 64 bytes and is defined by IEEE
18.2.10.3 AFCRID1 - Flow Control RAM Input Data 1
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h664
Write only
31
24 23
16 15
87
0
Content of Input Flow Control Frame[63:32]
Bit [31:0]
Content of flow control frame [63:32]
18.2.10.4 AFCR - Flow Control Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h670
Write/Read
31
16 15 14 13 12 10 9
0
XN FE AE XON_Thd
Bit [9:0]
Reserved
Bit [12:10]
XON_Thd
Defines the minimum # of free Frame Buffers before
transmitting XON flow control frame.
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