MDS212 Datasheet, PDF (41/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
10.1 External CPU Support
The control bus comprises of a 32-bit wide CPU bus and supports Big and Little Endian CPU byte ordering. The
standard microprocessors supported include:
• Intel 486 CPUs
• Motorola MPC860 and 801 CPUs.
• Intel i960Jx CPU
• MIPS processor with minimum conversion.
10.1.1 Power On/Reset Configuration
On power-up, the five Bootstrap bits, on Table 6, are used.
10.1.2 CPU Bus Clock Interface
The CPU Interface allows the CPU bus clock to operate at clock rates different from the system clock rate. The
CPU Bus Clock rate is always less than or equal to the System Clock rate.
Name
BS_BMOD
BS_RW
BS_SWM
BS_PSD
BS_RDYOP
Default
1
1
1
1
1
Functional Description
Bus Mode
Must be 0
Selects R/W Control polarity
0=R/W# 1=W/R#
Switch Mode (only in Managed Mode)
0=Managed Mode 1=Unmanaged Mode
Primary Device Enable (only in Unmanaged Mode)
0=Secondary Mode 1=Primary Mode
(The arbiter is activated in the chip with Primary Device.)
Option of merger the P_RDY# and P_BRDY#
1=Seperated P_RDY# and P_BRDY# pins
0=merged P_RDY# and P_BRDY# pin
Table 6 - Bootstrapping Options
10.1.3 Address And Data Buses
The CPU Interface provides separate, non-multiplexed address and data buses. The data bus is a synchronous,
32-bit bus that can receive 16 or 32-bit wide data. The Flash memory uses a 16-bit data bus. The data bus supports
32 bit wide data for managed and unmanaged modes. The address bus supports 10 [10:1] address bits for
managed and unmanaged modes. Each device occupies 2048 bytes of Input/Output space.
10.1.4 Bus Master
The nomenclatures “Master” and “Slave” refer to the device that possesses the CPU Interface, or Control Bus,
while the designations of “Primary” and “Secondary” refer to the device that possesses the Bus Arbiter. The primary
or secondary device is determined during Power On/Reset, bootstrap options, while the master or slave device
changes dynamically, and will be determined by the Arbiter.
In managed mode, the systems’ external CPU is the permanent master device. All other devices (e.g. the MDS212)
are designated as slave devices only. In unmanaged mode, the arbiter (located within the primary device) selects
one of the devices as the Master.
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