MDS212 Datasheet, PDF (37/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
8.0 The XPipe
The XPipe provides a high-speed link between systems utilizing two MDS212 devices. The XPipe incorporates a
32-bit-wide data pipe, with a high-speed point-to-point connection, and a full-duplex interface betweendevices.
While operating at a 100MHz, this interface can provide 3.2G bits per second (Gbps) of bandwidth per pipe in both
directions.
8.1 XPIPE Connection
Transmit FIFO
Source
Xmit
Ctrl
X_DO[31:0]
X_DCLKO
X_DENO
X_FCI
X_DI[31:0]
X_DCLKI
X_DENI
X_FCO
Receive FIFO
Recd
Ctrl
Target
Receive FIFO
Target
Recd
Ctrl
X_DI[31:0]
X_DCLKI
X_DENI
X_FCO
X_DO[31:0]
X_DCLKO
X_DENO
X_FCI
Transmit FIFO
Xmit
Ctrl
Source
MDS212
MDS212
Figure 7 - XPipe System Block Diagram for the MDS212
The XPipe interface employs 32 data signals and three control signals for each direction. The pin connections
between two MDS212 devices are depicted in Figure 7. These 32 data signals form a 32- bit-wide transmission
data pipe that carries XpressFlow messages to and from the devices. The direction of all signals are from the
source to the target device, except for the flow control signal, which sends messages in the opposite direction; from
the target to the source. The three control signals consist of a Transmit Clock signal, a Transmit Data Enable signal,
and a Flow Control signal.
The Transmit Clock signal (X_DCLKO), provides a synchronous clock to sample the data signals at the target
device. The source device provides the Transmit Data Enable signal (X_DENO) that envelops an entire XPipe
message (including the Header and the Payload) and is used to identify the message boundary from the received
data stream. The timing relationship between the data, clock, and data enable signals are described in the XPipe
Timing (section Section 8.2 “XPipe Timing” ”).
37
Zarlink Semiconductor Inc.