MDS212 Datasheet, PDF (83/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Bit [0:15]
Bit [31:16]
2-byte VLAN Type Code defined by IEEE 802.1Q VLAN Standard
Priority 4 level priority denoting by 2-bit for each
Mapping 8 level VLAN priorities to 4 level internal priorities.
18.2.8.2 AXSC - Transmission Scheduling Control Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h64C
Write/Read
31
12 11
87
43
0
QSW2
QSW1
QSW0
Bit [11:0]
QSW[2:0]
Transmission Queue Service Weight for queue 2, 1, & 0.
(4 bit each) Defines the service rate for each queue QR0-QR3
QR0 : QR1 : QR2 : QR3
QR0 = QSW0*(QSW1+1)* (QSW2+1)
QR1 = QSW1*(QSW2+1)
QR2 = QSW2
QR3 = 1
Note: Queue 0 has the highest priority. Queue Size is defined in the Queue Control Table.
18.2.8.3 ATTL - Transmission Timing Control
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h650
Write/Read
31
24
22 21
14 13
54
0
TXFIFO
Threshold[7:0]
depart_time
qmt_cnt
Bit [4:0]
Bit[13:5]
Bit [21:14]
TXFIFOT
Transmission queue aging time out counter
frame latest departure time
Transmission FIFO Threshold in Bytes (Default =0)
Unit=8Bytes
0= Cut Through at the destination 100M port
When the value does not equal zero, it indicates the port cannot
start sending frames out, until the TxFIFO reaches the
threshold or EOF.
18.2.9 MII Serial Management Channel
These registers are part of the Management Module. They allow the upper layer services to communicate with any
one of the PHYs that are connected to the Management Module through the serial interface.
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Zarlink Semiconductor Inc.