MDS212 Datasheet, PDF (70/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Bit [30]
PSD
Bit [31]
MRDY
Master Device Enable (Read only bit)
Default=1
1 =Primary
0 = Secondary
Option of merge the RDY and B_RDY as one pin (Read only bit)
Default=1
0 = merged pin
1 = separated pins
18.2.1.5 DCR3 - Interfaces Status Register
• Access:
• Address:
Zero-Wait-State,
h7CC
31
25 24
21 20
16 15
Direct Access, Read only
12 11
Que_Stat
87
4 3 20 1
Mem_Stat
Bit [3:0] Reserved
Bit [7:4] Mem_Stat
Bit [4]
BB
Bit [5]
RE
Bit [6]
WE
Bit [7]
Res.
Bit [11:8] Que_Stat
Bit [8]
IQ_Rdy
Bit [9]
IQ_Full
Bit [31:12] Reserved
Buffer Memory Interface Status
Buffer Memory Busy, CPU interface is busy accessing Memory
Read FIFO Empty, the FIFO that CPU interface reads is empty
Write FIFO Empty, the FIFO that CPU writes is empty
Reserved
Queue Manager Interface Status
CPU Input Queue is ready for CPU to write into queue
CPU Input Queue is full
18.2.1.6 MEMP - Memory Packed Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access, Write/Read
h7DC
31 30
17 16 15
NP
WCL
87
5
0
RCL
Bit [7:0] RCL
Bit [15:8] WCL
Bit [16] NP
Read Cycle Limit (Unit is system Clock).
Threshold of reads cycle time.
Write Cycle Limit (Unit is system Clock).
Threshold of writes cycle time.
Not Packed
NP=0 Enable the feature of
memory read/write packed.
Bit [31:17] Reserved
Default=16
Default=16
Default=0
NP=1 Disable, memory
access will be a pure
round-robin scheme.
70
Zarlink Semiconductor Inc.