MDS212 Datasheet, PDF (42/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Note: In unmanaged mode, the primary device may be the Master or the Slave. The master device is the bus
master (controls the bus), while the other device is a slave device.
10.1.5 Input/output Mapped Interface
The systems’ external CPU accesses the switch devices’ local memory using single-read/write or burst- read/write
I/O cycles. Burst I/O operations with auto address incrementing uses a 32-byte write data buffer and a 32-byte
cache read data buffer.
10.1.6 Interrupt Request
The CPU Interface accepts an Interrupt Request (IRQ) from each device connected to the interface, and supports
centralized interrupt arbitration and vector response. The interrupt output is an open-drain option with
programmable polarity.
10.2 Control Bus Cycle Waveforms
P_CLK
P_ADS#
P_RDY#
one-wait state _{P_A[10:1]}
Write cycle
wait
Read cycle
Burst
wait Read
wait Read Read Read Read
Sample
P_BRDY#
P_BLAST#
Read cycle = 8 clks
Figure 12 - Control Bus I/O and Flash Bus Access Operations
10.3 The CPU Interface in Unmanaged Mode
In unmanaged mode, the HISC processor of the Master device communicates with the slave device as a CPU
function. Three registers and one flag are used to communicate between the HISC processor and the CPU
Interface.
10.3.1 Arbiter
The arbiter of the XpressFlow MDS212 is an internal logic device used to determine which device will function as
the master device. The connections between the master device, slave device, and the CPU are used for debugging
purposes only (see Figure 13).
During Power On/Reset, the bootstrap pin, BS_PSD, determines which device will be the primary and activates the
arbiter of that device. At most, three devices, two MDS212 devices and one CPU, can operate on the CPU
Interface at the same time.
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Zarlink Semiconductor Inc.