MDS212 Datasheet, PDF (43/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Each device may request access to the CPU Interface by sending a Request signal to the arbiter. The arbiter, then
sends a Grant signal acknowledging which device has been chosen.
CPU
Only for Debug
P_GNTC
P_REQC
MDS212
Primary
Master the
State
Machine
Bus
Request
Bus Grant
Arbiter
Chip Select
P_REQ1
P_GNT1
Master the
State
Machine
MDS212
Secondary
Figure 13 - Block Diagram of the Arbiter
Note: In unmanaged mode, the CPU is used only for debugging purposes and cannot be involved in switching
decisions or management activities.
An arbitrate scheduler, located within the arbiter, decides which device functions as the Master device. If the Master
is the secondary device, the arbiter will send a Grant signal and a Chip Select (P_CS) signal to the device. If the
Master is the primary device, the Grant signal is sent directly to the Master State Machine (MSM) by an internal
signal. The scheduler then performs a round robin configuration and allows each device to be the Master device.
Note: During Power On/Reset, the arbiter always selects the primary device to be master device.
10.4 CPU Interface In Managed Mode
The CPU Slave State Machine (SSM) accepts Address Strobe (P_ADS#), Chip Select (P_CS#), and Bus- Data
Ready (P_RDY#) signals as ready state signals of a CPU cycle.
10.4.1 CPU Access
The 32-bit CPU bus interface supports both Big and Little Endian CPUs. The difference between Big and Little
Endian is the byte swapping when CPU write data to external memory. Table 7 below summarizes the byte
swapping operation and Figure 14 illustrates an example of bytes swapping.
If using Little Endian
If using Big Endian
Bit[1] must be ‘0’ for register of
MWARS, MRARS, MWARB,
MRARB
Bit[1] must be ‘1’ for register of
MWARS, MRARS, MWARB,
MRARB
No byte swapping for CPU data
write in or read out to/from
MWDR, MRDR registers
Automatic Byte swapping for CPU
data write in or read out to/from
MWDR, MRDR registers
Table 7 - Little and Big Endian Byte Swapping Operation
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