MDS212 Datasheet, PDF (26/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
The free handle pool must be initialized via the register group CPUIRCMD, CPUIRDAT, CPUIRRDY, type BMCT,
before device operation. The Buffer Manager Control Table (BMCT) is the pool of free handles. At reset, the BMCT
is empty. Prior to device operation, free handles must be written to the BMCT. The user must write the integers
{0,1,2,3, … K-1} to the BMCT one-at-a-time, where K is the maximum number of buffers. The value of K depends
on the external memory size and partition, and it can be 128, 256, 512, or 1024.
If all buffers are used, no more frames can enter the device. The Frame Engine keeps buffer counters that limit the
number of buffers occupied by frames destined for each output port. If a buffer counter exceeds a programmable
threshold, its associated output port is “blacklisted.” Entering frames destined to this output port are discarded, until
the counter goes below the threshold. This threshold is programmed via registers BCT and BCHL. These counters
prevent complete depletion of buffers due to an overloaded port, thus allow frames destined for non-congested
ports to enter the system. This effectively avoids head-of-line blocking.
The Frame Engine also keeps a buffer counter for multicast traffic types. The buffers occupied by incoming
multicast frames are limited. This prevents multicast frames from blocking unicast ones from entering the system.
The threshold for multicast traffic types is programmed via register MBCR.
5.0 Frame Buffer Memory
5.1 Frame Buffer Memory Configuration
The MDS212 system utilizes external SRAM for its Frame Buffer Memory configuration, where the size of memory
supported is ½ MB, 1MB and 2MB configurations. The following table shows four memory configuration examples
for the MDS212 system:
SRAM Type
64Kx32
128Kx32
One Bank
Two Bank
Address
Size
Address
L_A[18:3]
½MB
L_A[19:3]
L_A[19:3]
1MB
L_A[20:3]
Table 1 - Type and Size of Memory Chips
Size
1M
2M
The following figure shows the connections between the Frame Buffer Memory and the MDS212 for one-bank and
two-bank memory configurations:
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