MDS212 Datasheet, PDF (95/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU
• Access:
Non-Zero-Wait-State, Direct Access,
Write/Read
• Address:
h594
• The Frame Engine sets this ready bit to notify the CPU that the requested data is ready to read.
31
Bit [0]
Bit [31:1]
R_RDY
Reserved
1
0
RDY
Data in Data registers is ready for CPU Read
18.2.11.11 LEDR - LED Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h598
Write/Read
31 30
SS
28 27 26 25 24 23
16 15
87
0
LCK
HT
UDEF3
UDEF2
UDEF1
Bit [7:0]
Bit [15:8]
Bit [23:16]
Bit [25:24]
Bit [27:26
Bit [30:28]
Bit [31]
UDEF1
UDEF2
UDEF3
HT
LCLK]
Reserve
SS
User defined information status 1 for debug purpose
User defined information status 2 for debug purpose
User defined information status 3 for debug purpose
Holding time for LED signal (Default=00)
00=8msec
01=16msec
10=32msec
11-64msec
LED Clock frequency (Default=00)
00=100M/8=12.5Mhz 01=100M/16=6.25Mhz
10=100M/32=3.125Mhz11=100M/64=1.5625Mhz
Start Shift out the status bits out from the master device. This bit
has no effect on slave chip.
Note: UDEF1-UDEF3 are used for debug purpose. The contents of UDEF1-3 are loaded by CPU and the usage of
these are up to software.
18.2.12 Ethernet MAC Port Control Registers
• One set for each Ethernet MAC Port [11:0]
18.2.12.1 ECR0 - MAC Port Control Register
• Access:
• Address:
h000
h040
h080
h0c0
h100
h140
h180
Non-Zero-Wait-State,
h0x0*4
ECR0_p0
ECR0_p1
ECR0_p2
ECR0_p3
ECR0_p4
ECR0_p5
ECR0_p6
Direct Access,
x: port n (n=0 - 11)
Write/Read
95
Zarlink Semiconductor Inc.