MDS212 Datasheet, PDF (78/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
18.2.6 Switching Control Register
18.2.6.1 HPCR - HISC Processor Control Register
• Access:
• Address:
Non-Zero-Wait-State, Direct Access,
h6C0
31
Write/Read
3 21 0
RS LD HT
Bit [0]
Bit [1]
Bit [2]
Bit [31:3]
HT
LD
RS
Reserved
Halt the HISC processor from execution Not Apply for
non-managed mode (It can be fixed in next cut.)
Power-up default = 1
Switch the Micro-Code Memory from instruction fetch mode to
down-loading mode
Reset IP to 0 – (Write only bit) (This bit is auto reset to 0 after
IP is reset to 0)
RS
LD
HT State
Description
1
0
1
INIT Initialization State: Stopped HISC execution, reset IP to 0.
0
0
1 HALT Halt State: Stopped HISC execution, waiting for HT=0
0
1
X LOAD Micro-Code Loading State: Stopped HISC execution, increment IP for
every Wr/RD to HMPC.
1
0
0 START Start State: Reset IP=0, and start HISC execution.
0
0
0 EXEC Execution State: Continue HISC execution without reset IP.
1
1
X
-- Illegal State
Table 12 - HPCR - HISC Processor Control Register
18.2.6.2 HMCL0 - HISC Micro-code Loading Port – Low
• Access:
Non-Zero-Wait-State, Direct Access,
• Address:
h6C4
• Loading micro code into HISC.
Write/Read
31
Bit [31:0]
HISC
Instruction
Word [31:0]
19
0
HISC Instruction Word [31:0]
HISC Instruction Word has total 40 bit-wide. Needs to be
broken into two registers.
78
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