MDS212 Datasheet, PDF (91/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
Usage: These masks are used to prevent flooded or multicast packets from being transmitted out with more
than one port on a trunk. The Trunking Hash Key is used to select the proper mask (for load distribution). The
mask value will be set up to mask off all but one port within each trunk group.
18.2.11.4 IPMCAS - IP Multicast MAC Address Signature
Usage: For following four registers IPMCAS0, IPMCAS1, IPMCMSK0 and IPMCMSK1, are used to distinguish
between IP multicast traffic and regular multicast. The MAC for IP multicast are h”01:00:5e:00:00:00” to h”
01:00:5e:7f:ff:ff” And the MASK for IPMC is: h“ff:ff:ff:80:00:00”.
• The 6-byte of IP multicast MAC Address is stored in two 32-bit registers
• IPMCAS0
IP Multicast MAC Address Byte [3:0]
• Address:
h5E8
• IPMCAS1
IP Multicast MAC Address Byte [5:4]
• Address:
h5EC
• Access:
Non-Zero-Wait-State, Direct Access, Write/Read
IPMCAS0
IPMCAS1
31
24 23
16 15
MAC 3
MAC 2
MAC 1
MAC 5
87
0
MAC 0
MAC 4
• These two registers define the MAC address signature of IP multicast.
• Default = h” 01:00:5e:7f:ff:ff”
18.2.11.5 IPMCMSK - IP Multicast MAC Address Mask
• The 6-byte of IP multicast MAC Mask is stored in two 32-bit registers
• IPMCAS0 IP Multicast MAC Mask Byte [3:0]
• Address:
h5F0
• IPMCAS1 IP Multicast MAC Mask Byte [5:4]
• Address:
h5F4
• Access:
Non-Zero-Wait-State, Direct Access, Write/Read
IPMCMSK0
IPMCMSK1
31
24
MASK 3
23
16 15
MASK 2
MASK 1
MASK 5
87
0
MASK 0
MASK 4
• These two registers define the MAC Mask of IP multicast.
• Default = h“ff:ff:ff:80:00:00”.
18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read
• Access:
• Address:
Non-Zero-Wait-State,Direct Access,Read only
h580
Usage: When CPU requests a free FDB to write a frame, it must request a free FCB via this register. The register
contains a free handle of FCB, which also pointer to a free FDB.
• CPU reads FCB Handle: (When the CPU write FDB, it requires a FDB handle first).
• CPU checks CFCBHDL[31],H_RDY ready or not. If so, CPU gets the FCB Handle from CFCBHDL[9:0]
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