MDS212 Datasheet, PDF (73/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
18.2.3.2 MRARS - Memory Read Address Register - Single Cycle
Access: Zero-Wait-State,via FIFO,Write
Address:h784
31
28 27 24
23
BE[3:0]
0001
22
21 20
I/E
Address MA[20:2]
3 2 ₁₀
SP LK
Bit [0]
LK
Bit [1]
Bit [20:2]
Bit [21]
Bit [22]
SP
MA [20:2]
Reserved
I/E
Bit [27:23]
Bit [31:28]
Count
BE [3:0]
Lock Flag memory
LK=0 Unlock
LK=1 Lock
Swap Byte Order
Buffer memory address Bit [20:2] – (Bit [1:0] = 00)
Indicate the Address is Internal or External memory
I/E=0 Internal memory
I/E=1 External memory
Must be 00001
Byte lane enables.
18.2.3.3 Address Registers For Burst Cycle
• Two 32-bit burst size registers share a common format
• MWARB Memory Address Register – Burst Write (in D-words) – Maximum 8 D-words
• Address:
h788
• MRARB Memory Address Register – Burst Read (in D-words) – Maximum 8 D-words
• Address:
h78C
• Access: Zero-Wait-State,
via FIFO,
Write
31
28 27 24
23
22
21 20
3 2 10
Count
I/E
Address MA[20:2]
SP LK
Bit [0]
LK
Bit [1]
Bit [2]
Bit [20:2]
Bit [21]
Bit [22]
SP
Reserved
MA [20:2]
Reserved
I/E
Lock Flag
LK=0 Unlock
Swap Byte Order
LK=1 Lock
Buffer memory address Bit [20:2] – (Bit [1:0] = 00)
Indicate the Address is Internal or External memory
I/E=0 Internal memory
I/E=1 External memory
73
Zarlink Semiconductor Inc.