MDS212 Datasheet, PDF (63/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Tag
Description
Address
DCR3
Interface Status Register
MEMP Memory packed Register
2. Interrupt Controls
ISR
Interrupt Status Register-Unmasked
ISRM
Interrupt Status Register-Masked
IMSK
Interrupt Mask Register
IAR
Interrupt Acknowledgment Register
3. Buffer Memory Interface
MWARS Memory Write Addr. Reg. - Single Cycle
MRARS Memory Read Addr. Reg. - Single Cycle
MWARB Memory Burst Write Address Register
MRARB Memory Burst Read Address Register
MWDR Memory Write Data Register
MRDR Memory Read Data Register
VTBP
VLAN ID & MAC member Table Base Pointer
MBCR
Multicast Buffer Control Register
RAMA
RAM block access Register
Reserve Must Set to “0x0001 0008”
Reserve Must Set to “0x0001 0000”
4. Frame Control Buffers Management
FCBSL FCB Stack Size Limit
FCBST Frame Ctrl Buffer Stack - Buffer Low Threshold
BCT
Buffer Counter Threshold
BCHL
Buffer Counter Hi-Low Selection
5. Queue Management
CINQ
CPU Input Queue
COTQ
CPU Output Queue
6. Switching Control
HPCR
HISC Processor Control Register
HMCL0 HISC Micro-Code Loading Port-Low
HMCL1 HISC Micro-Code Loading Port-High
HPRC
HISC Priority Control Register
MCS0R Micro Sequence 0 Register
MCS1R Micro Sequence 1 Register
Table 9 - MDS212 Register Map (continued)
7CC
7DC
7E0
7E4
7E8
7EC
780
784
788
78C
790
794
798
79C
7A0
7B8
7BC
740
744
74C
750
708
70C
6C0
6C4
6C8
6D0
6D4
6D8
Data Sheet
W/R
--/R
W/R
--/R
--/R
W/R
W/--
W/--
W/--
W/--
W/--
W/--
--/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/--
--/R
W/R
W/R
W/R
W/R
W/R
W/R
63
Zarlink Semiconductor Inc.