MDS212 Datasheet, PDF (36/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
7.5 Communication Between Management CPU and HISC
The HISC serves as an intermediary communication channel between the switching hardware and the external
management CPU. There are two communication mechanisms provided for messages exchanged between the
management CPU and HISC.
7.5.1 CPU-HISC Communication Using Queues
The first communication mechanism is a pair of Input and Output Queues between the HISC and management
CPU. The management CPU input/output queue is a very efficient mechanism for a single 32-bit data exchange
between the HISC and management CPU. In general, a management frame, i.e., Bridged Data Protocol Units
(BDPU), is forwarded directly from the HISC to the management CPU via the CPU Output Queue. Small
management requests, less than 24 bits, are delivered to the HISC via the CPU Input Queue.
7.5.2 Mailbox
The second communication mechanism is a hardware mailbox that can support variable size messages,
exchanged between the management CPU and the HISC. A major use of the mailbox is to exchange information
required for updating the switching database.
7.5.2.1 CPU-HISC Mail
When the management CPU sends a mail message to the HISC, the CPU acquires an address of a free mail from
the free mail list (via register AFML), it writes the mail content to the given memory address. Afterward, it sends the
mail to the HISC via the Mailbox Access (AMBX) Register. Whenever a management mail message is received, an
event is generated to inform the HISC to process the mail message.
7.5.2.2 HISC-CPU Mail
When a mail message arrives from the HISC, the mailbox hardware sends an interrupt, namely “Mail Arrive”
(MAIL_ARR), to the CPU. The CPU can then access the mail via the Mailbox Access Register (AMBX). At this
point, the CPU reads the mail handle and retrieves the contents of the mail from the AMBX Register.
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