MDS212 Datasheet, PDF (40/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
• It provides independent 2 bit wide (di-bit) transmit and receive data paths.
• It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
Data Sheet
Signal Name
REF_CLK
M[0:11]_CRS_DV
M[0:11]_RXD[1:0]
M[0:11]_TX_EN
M[0:11]_TXD[1:0]
M[0:11]_RX_ER
Direction
(with respect to the PHY)
Input or Output
Input
Input
Output
Output
Input (Not required)
Direction
(with respect to the MAC)
Synchronous clock reference for
receive, transmit and control interface
Carrier Sense/Receive Data Valid
Receive Data
Transmit Enable
Transmit Data
Receive Error
Table 5 - RMII Specification Signals
10.0 The Control Bus
The CPU Interface, or Control Bus, provides the communication path between the system CPU and all other key
components within the switch (i.e. the HISC). It operates in two modes: managed mode, where it utilizes an
external CPU, and unmanaged mode, where an external CPU does not exist.
In Managed mode, the CPU Interface provides the communication path between the systems’ external CPU and
the HISC, Frame Buffer Memory (SRAM) or another MDS212. See Figure 10.
Control Bus
MDS212
MDS212
CPU
Flash
Memory
Figure 10 - CPU Interface Configuration in Managed Mode
In unmanaged mode, the CPU Interface provides the communication path between the Switch Devices
and Flash Memory, and between any two MDS212 Switches. See Figure 11.
Control Bus
Primary DEV
MDS212
Arbitrator
Secondary DEV
MDS212
Flash
Memory
Figure 11 - Control bus Configuration in Unmanaged Mode
40
Zarlink Semiconductor Inc.