MDS212 Datasheet, PDF (71/111 Pages) Zarlink Semiconductor Inc – 12-Port 10/100Mbps Ethernet Switch

MDS212
Data Sheet
18.2.2 Interrupt Control Registers
• Four 32-bit Control Registers.
• ISR
Interrupt Status Register Identify the unmasked interrupt request sources
• Access: Zero-Wait-State,
Direct Access,
Read only
• Address: h7E0
• ISRM
masking
Masked Interrupt Status Reg.
Identify the sources of interrupt with
• Access:
Zero-Wait-State,
Direct Access,Read only
• Address:
h7E4
• IMSK
masked
Interrupt Mask Register
Defines the interrupt sources to be
• Access:
Non-Zero-Wait-State,
Direct Access,Write/Read
• Set bits to 1 to mask the corresponding interrupt sources
• Address:
h7E8
• IAR
Interrupt Acknowledgment Reg. Clear the interrupt request bits
• Access:
Non-Zero-Wait-State,
Direct Access,Write only
• Set bits to 1 to clear the corresponding interrupt sources
• Address:
h7EC
All 4 registers have a common register format and bit assignment
31 25 24 23
11 10 9
MCT
8 76 5 4
MAC_Port Interrupt
32
FML
MAIL
1
0
BP FCBL DBR BSR CPQ
Interrupt MAC port mapping bit/port Interrupt Source
Interrupt Sources (The following bits need to be redefined.)
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
CPU_Q_Out
BSR
Double R
FCB_Low
HISC_BP
Reserved
Reserved
MAIL_ARR
HISC_TO
Reserved
FML_Av
Bit [23:11] MAC_PORT
Bit [24] MCT
Bit [31:25] Reserved
CPU output queue level interrupt
Bad switch response
Double Release
FCB Low
HISC instruction pointer matched with Breakpoint Register
Mail arrived from HISC
HISC Timeout Interrupt
Link manager informs CPU that at least 16 Free Mail entry
available after CPU encounters empty Free Mail list situation.
Interrupt from MAC ports
Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12.
Search Engine found looped MCT Chain.
Note: MAIL_ARR, CPU_Q_Out, and interrupts cannot be cleared by the CPU. They will be cleared whenever their
queues are emptied.
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Zarlink Semiconductor Inc.