DS823 Datasheet, PDF (9/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 2: Sink Control and Status Interface Signals (Cont’d)
Name
Direction Clock Domain
Description
SnkBusErrStat[7:0]
Output
Sink Bus Error Status. Each bit of this bus corresponds to a
specific Sink Bus Error condition and is asserted concurrently
with SnkBusErr. The error conditions detected are reported
as follows:
• SnkBusErrStat [0]: Minimum SOP spacing violation.
• SnkBusErrStat [1]: Control word with EOP not preceded
by a data word.
• SnkBusErrStat [2]: Payload control word not followed by a
data word.
RDClkDiv_User • SnkBusErrStat [3]: DIP4 error received during training or
on idles.
• SnkBusErrStat [4]: Reserved control words received.
• SnkBusErrStat [5]: Non-zero address bits on control
words received (except on payload and training control
words).
• SnkBusErrStat [6:7]: Reserved bits (tied low).
When dynamic phase alignment configuration is used,
SnkBusErrStat can be used to monitor the alignment status.
See the SPI-4.2 User Guide for more information.
SnkTrainValid
Output
Sink Training Valid. Active high signal that indicates that a
valid training pattern has been received. This signal is
RDClkDiv_User asserted for the duration of the training pattern (20 SPI-4.2
bus cycles or 5 RDClkDiv_User clock cycles), if the training
pattern received is successfully decoded.
SnkDIP2ErrRequest
Input
Sink DIP2 Error Request. This is an active high signal that
RDClkDiv_User
requests an incorrect DIP-2 to be sent out of the RStat bus.
When this signal is asserted, the Sink Status FIFO responds
by inverting the next DIP2 value that it transmits.
Sink AXI4-Stream FIFO Interface
The Sink AXI4-Stream FIFO interface provides data received on the SPI-4.2 interface to the user's logic.
In addition to the 64-bit or 128-bit data word, control and status signals (including error signals) are
associated with a particular channel or packet. For example, these status signals will flag improper
packet format, DIP4 error, and FIFO Status. Table 3 provides the Sink FIFO interface signals and a
description of each.
Table 3: Sink AXI4-Stream FIFO Interface Signals
Name
Direction
Description
M_AXIS_SNKFF_ACLK
Input
Sink FIFO Clock. All Sink FIFO Interface signals are
synchronous to the rising edge of this clock.
M_AXIS_SNKFF_ARESETN
Input
Sink FIFO Reset. Active low signal that enables the user to reset
the Sink FIFO and the associated data path logic. This enables
the FIFO to be cleared while remaining in-frame.The reset signal
can be asserted asynchronously, but deassertion must be
synchronous after the rising edge of ACLK. See the AMBA®
AXI4-Stream Protocol specification for more information.
M_AXIS_SNKFF_TREADY
Input
Sink FIFO User Ready Handshake. Indicates the user is ready
to accept streaming data. When both TREADY and TVALID are
asserted on the rising edge of M_AXIS_SNKFF_ACLK, one data
beat is transferred.
DS823 July 25, 2012
www.xilinx.com
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Product Specification