DS823 Datasheet, PDF (29/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 12: Dynamic Phase Alignment SIgnals (Cont’d)
Signal Name
Direction Clock Domain
Description
SnkDPAClkDlyCe
(optional)
Output
Phase Alignment IDELAY Clock Enable. Active
high signal used to enable the increment of the
RDClkDiv_User
IDELAY inserted in the RDClk path of the external
sink clocking module.This option is only available
when the “DPA Clock Adjustment” feature is
enabled.
SnkDPAClkDlyInc
(optional)
Output
Phase Alignment IDELAY Increment. Active high
signal used to increment the delay value of the
RDClkDiv_User
IDELAY inserted in the RDClk path of the external
sink clocking module.This option is only available
when the “DPA Clock Adjustment” feature is
enabled.
Static Alignment
The Sink Core performs static alignment by shifting the clock relative to the 16-bit data such that the
incoming clock edge is centered to the data eye of RDat/RCtl. For designs using global clocking
distribution, this alignment can be performed by using the IDELAY function or an MMCM. For designs
using regional clocking distribution, the IDELAY function is used to shift the clock in relation to the
data bits.
Static Alignment Using IDELAY
Static alignment can be performed using the IDELAY function of the ISERDES for either global or
regional clocking distribution. The ability of the IDELAY function to delay its input by small
increments enables the internal RDClk to be shifted relative to the sampled data. For statically aligned
systems, the delay chain length is a critical path of the system. The static alignment solution assumes
that the PCB is designed with precise delay and impedance matching for all LVDS differential pairs of
the data bus. In this case, the primary alignment mechanism is time, shifting the internal RDClk
relative to the data bits using the IDELAY function.
Static Alignment Using MMCM
The core also supports legacy static alignment, which uses the MMCM to phase shift the RDClk. The
MMCM-based static alignment is only supported for global clocking distribution. The ability of the
MMCM to shift the internal clock enables RDClk to be shifted relative to the sampled data. For
statically aligned systems, the MMCM output clock phase offset is a critical part of the system. The
static alignment solution using MMCM assumes that the PCB is designed with precise delay and
impedance matching for all LVDS differential pairs of the data bus. This assumption is critical as the
MMCM does not compensate for deviations in delay between bits.
Clocking Options
The SPI-4.2 solution provides several clocking options for Sink and Source cores that provide the
flexibility to select the most suitable option for any system. Different clock resources are used,
depending on the clocking option selected. Table 13 through Table 15 provide the clocking resource
count for each clocking option (not including the user interface FIFO clocks) for Virtex-7 and Kintex-7
FPGAs.
DS823 July 25, 2012
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29
Product Specification