DS823 Datasheet, PDF (20/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Source AXI4-Stream FIFO Interface
The Source AXI4-Stream FIFO interface stores data from the user logic to be transmitted on the SPI-4.2
interface. In addition to the 64-bit or 128-bit data word, there are control and status signals associated
with a particular channel or packet. Table 8 defines the Source FIFO signals.
Table 8: Sink AXI4-Stream FIFO Interface Signals
Name
Direction
Clock Domain
Description
S_AXIS_SRCFF_ACLK
Input
Source FIFO Clock. All Source FIFO
n/a
Interface signals are synchronous to the
rising edge of this clock.
S_AXIS_SRCFF_ARESETN
Input
Source FIFO Reset. Active low signal
that enables the user to reset the Source
FIFO and the associated data path logic.
This enables the FIFO to be cleared while
S_AXIS_SRCFF_ACLK
remaining in-frame. The reset signal can
be asserted asynchronously, but
deassertion must be synchronous after
the rising edge of ACLK. See the AMBA
AXI4-Stream Protocol specification for
more information.
S_AXIS_SRCFF_TREADY
Output
Source FIFO Core Handshake.
Indicates the core is ready to accept
streaming data. When both TREADY and
TVALID are asserted on the rising edge
S_AXIS_SRCFF_ACLK of S_AXIS_SRCFF_ACLK, one data beat
is transferred into the core. De-assertion
of TREADY indicates the Source core
has reached the AlmostFull threshold set
by the parameter SrcAFThresAssert.
S_AXIS_SRCFF_TVALID
Input
Source FIFO User Handshake.
Indicates the user is presenting valid
streaming data. When both TREADY and
TVALID are asserted on the rising edge
of S_AXIS_SRCFF_ACLK, one data beat
is transferred into the core. When
S_AXIS_SRCFF_ACLK
asserted (active high), this signal
indicates that the information on
S_AXIS_SRCFF_TDATA,
S_AXIS_SRCFF_TID,
S_AXIS_SRCFF_SOP,
S_AXIS_SRCFF_TLAST,
S_AXIS_SRCFF_TKEEP, and
S_AXIS_SRCFF_ERR are valid.
S_AXIS_SRCFF_TID[7:0]
Input
Source FIFO Channel Address.
S_AXIS_SRCFF_ACLK Channel number associated with the data
on S_AXIS_SRCFF_TDATA.
S_AXIS_SRCFF_TDATA[63:0]
or
S_AXIS_SRCFF_TDATA[127:0]
Input
Source FIFO Data. The Source FIFO
data bus. Bit 0 is the LSB. The core can
S_AXIS_SRCFF_ACLK
be configured to have a 64-bit or a 128-bit
interface. The 128-bit interface enables
the user to run at half the clock rate
required for a 64-bit interface.
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DS823 July 25, 2012
Product Specification