DS823 Datasheet, PDF (31/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
• Kintex-7 FPGAs -1, -2, and -3 devices up to 1Gbps (depending on speed grade) on the SPI-4.2
Interface and 250MHz on the User Interface (M_AXIS_SNKFF_ACLK and
S_AXIS_SRCFF_ACLK clocks).
• Virtex-7 FPGAs -1, -2, and -3 devices up to 1.25 Gbps (depending on speed grade) on the SPI-
4.2 Interface and 312 MHz on the User Interface (M_AXIS_SNKFF_ACLK and
S_AXIS_SRCFF_ACLK clocks).
Hardware validation for 7 series devices is pending.
Device Utilization
Table 16 lists the Block RAM, LUTs, and FFs counts for Virtex-7 and Kintex-7 devices.
Table 16: Core Utilization – Virtex-7/Kintex-7 Devices
Core Configuration
Block RAM
64-bit Static Alignment
3 (36k block RAM)
9 (18k block RAM)
64-bit Dynamic Alignment (default)
3 (36k block RAM)
9 (18k block RAM)
128-bit Static Alignment
3 (36k block RAM)
13 (18k block RAM)
128-bit Dynamic Alignment (default)
3 (36k block RAM)
13 (18k block RAM)
LUTs
4050
5020
4670
5640
FFs
4330
4972
4775
5425
Performance in Virtex-7 FPGAs (Preliminary)
Table 17 contains the performance numbers for the SPI-4.2 cores that target Virtex-7 devices.
Table 17: Performance in Virtex-7 Devices
Alignment Type
Speed
Performance⁽¹⁾
Grade _{Sink Core with Global Clocking Sink Core with Regional Clocking}
Static⁽²⁾
-1, -2, -3
622-700Mbps
622-700Mbps
Dynamic (source core with
regional clocking)
-1
622-900Mbps
622-1.1Gbps
Dynamic (source core with
regional clocking)
-2
622-1.1Gbps
622-1.2Gbps
Dynamic (source core with
regional clocking)
-3
622-1.25Gbps
622-1.25Gbps
Dynamic (source core with
global clocking)
-1, -2
622Mbps-900Mbps
622Mbps-900Mbps
Dynamic (source core with
global clocking)
-3
622Mbps-1Gbps
622Mbps-1Gbps
1. Performance numbers shown use Virtex-7 FPGA High Performance (HP) I/O. Use of High Range (HR) I/O is
supported but may limit upper bound of performance range. See DS183, Virtex-7 FPGAs Data Sheet: DC and
Switching Characteristics for supported performance ranges using HR I/O. Between this document and DS183, the
SPI-4.2 core is limited to the smaller of the two performance numbers.
2. When the sink core is configured with static alignment, only regional clocking is supported on the source core.
DS823 July 25, 2012
www.xilinx.com
31
Product Specification