DS823 Datasheet, PDF (4/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Figure 2 shows input and output signals and the functional blocks of the Sink core. The interface
signals to each of the functional modules are described in detail in Core Interfaces, page 6.
X-Ref Target - Figure 2
Sink
Control
and Status
Interface
Reset_n
SnkEn
SnkOof
SnkBusErr
SnkBusErrStat[7:0]
SnkTrainValid
SnkDIP2ErrRequest
SnkIdelayCtlRdy
SnkDPA* (32 bits)
SnkDPAPhaseAlignRequest
SnkDPAPhaseAlignComplete
AXI SPI-4.2 Sink Core
Sink
User
Clocking
Interface
RDClk0_User
RDClkDiv_User
SnkClksRdy_User
Sink
AXI4-Stream
FIFO
Interface
M_AXIS_SNKFF_ACLK
M_AXIS_SNKFF_ARESETN
M_AXIS_SNKFF_TREADY
M_AXIS_SNKFF_TVALID
M_AXIS_SNKFF _TDATA[ 63:0] or [127 :0]
M_AXIS_SNKFF _TKEEP[ 7:0] or [15:0]
M_AXIS_SNKFF_TID[7:0]
M_AXIS_SNKFF_SOP
M_AXIS_SNKFF_TLAST
M_AXIS_SNKFF_ERR
M_AXIS_SNKFF_PAYLOADERR
M_AXIS_SNKFF_DIP4ERR
M_AXIS_SNKFF_PAYLOADDIP4
M_AXIS_SNKFF_BURSTERR
SNKFF_ALMOSTFULL_N
SNKFF_OVERFLOW_N
Sink
Data FIFO
Sink
Data Receive
RDClk
RDat[15:0]
RCtl
Sink
SPI-4.2
Interface
Sink
AXI4-Lite
Control
Interface
AXI _SNK_ACLK
AXI _SNK_ARESETN
SNK_BRESP_ERR[7:0]
AXI _SNK_ARREADY
AXI _SNK_ARVALID
AXI _SNK_ARADDR[9:0]
AXI _SNK_RREADY
AXI _SNK_RVALID
AXI _SNK_RDATA[31:0]
AXI _SNK_AWREADY
AXI _SNK_AWVALID
AXI _SNK_AWADDR[9:0]
AXI _SNK_WREADY
AXI _SNK_WVALID
AXI _SNK_WDATA[31:0]
AXI _SNK_WSTRB[3:0]
AXI _SNK_BREADY
AXI _SNK_BVALID
RSClk
RStat[1:0]
Sink
AXI4-Lite
Memory Space
Sink
Status Transmit
Figure 2: Sink Core Block Diagram and I/O Interface Signals
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DS823 July 25, 2012
Product Specification