DS823 Datasheet, PDF (2/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Applications
The SPI-4.2 (PL4) interface core enables the connection of physical-layer devices to link-layer devices in
10 Gbps POS, ATM, and Ethernet applications. The symmetric interface can be used to implement both
the PHY and Link layer.
Figure 1 shows the core in a typical link-layer application.
Driven by the improved efficiencies and lower cost-per-Mbit of Packet-over-SONET/SDH, the core is
ideally suited for line cards in gigabit routers, terabit and optical cross-connect switches, and for a wide
range of multi-service DWDM and SONET/SDH-based transmission systems.
The OIF SPI4-02.1 interface is widely used to connect network processors (such as the Intel IXP2800)
with OC-192 framers and mappers, as well as Gigabit and 10-Gigabit Ethernet data link MACs. The
Xilinx SPI-4.2 core is an implementation of this high-performance, low-pin-count data transfer protocol
that is ideally suited for these applications.
X-Ref Target - Figure 127
SPI-4.2
Interface
7 Series Device
SPI-4.2 Sink Core
User
Interface
Rx Data Path
SPI-4.2 PHY
Layer Device
(7 Series Device
or
ASSP)
Rx Status Path
Tx Data Path
Tx Status Path
SPI-4.2
Sink
Interface
User
Sink
Interface
SPI-4.2 Source Core
SPI-4.2
Source
Interface
User
Source
Interface
User’s Logic
(Link Layer
Processor)
Figure 1: SPI-4.2 Core in a Typical Link-Layer Application
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DS823 July 25, 2012
Product Specification