DS823 Datasheet, PDF (28/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
SPI-4.2 training pattern to achieve word alignment (bus deskew). The bus deskew phase removes any
skew induced by the independent bit sampling or bus skew on the PCB or backplane. Table 12 defines
the Dynamic Phase Alignment signals.
Table 12: Dynamic Phase Alignment SIgnals
Signal Name
Direction Clock Domain
Description
SnkDPAPhaseAlignComplete
Output
RDClkDiv_User
Phase Alignment Complete. Active high signal
that indicates phase alignment is complete.
SnkDPAPhaseAlignRequest
Input
Phase Alignment Request. Initial DPA
commences by asserting and deasserting
RDClkDiv_User
PhaseAlignRequest. DPA starts on a high-to-low
transition. When PhaseAlignRequest transitions
from low-to-high SnkOof will be driven high (core
goes out of frame).
SnkDPAFailed
Output
Phase Alignment Failed. Active high signal that
RDClkDiv_User indicates phase alignment has failed at the end of
the alignment sequence.
SnkDPARamAddr [5:0]
Output
Phase Alignment RAM Address. Bus indicating
RDClkDiv_User the ISERDES tap value that corresponds to the
data on SnkDPARamData.
SnkDPARamData [16:0]
Output
Phase Alignment RAM Data. Initial data collected
during alignment. Used to find the valid data
window for each bit of the SPI-4.2 bus. An active
high on the bus indicates that sampling on the
RDClkDiv_User ISERDES tap corresponding to SnkDPARamAddr
will result in sampling within a valid data window.
Each index corresponds to a bit on the SPI-4.2 bus;
RDat(0) is index 0, RDat(1) is index 1, ..., RCtl is
index 16.
SnkDPARamValid
Output
Phase Alignment RAM Valid. Active high signal
RDClkDiv_User indicating the information on SnkDPARamData and
SnkDPARamAddr is valid.
SnkCDPAHalt
(optional)
Input
Phase Alignment DPA Halt. Active high signal that
RDClkDiv_User enables the user to halt the pointer adjustment of
continuous DPA operation.
SnkDPADiagWin
(optional)
Input
Phase Alignment DPA Diagnostics. Active high
signal that enables the user to find the valid data
window during operation for each bit of the SPI-4.2
RDClkDiv_User bus. After the SnkDPADiagWin is pulsed, the valid
data window information is presented on
SnkDPARamAddr [5:0] and SnkDPARamData
[16:0] when SnkDPARamValid is asserted.
SnkDPAAddrRst
(optional)
Input
Phase Alignment DPA Address Reset. Active
RDClkDiv_User high signal that clears the SnkDPARamAddr
counter.
SnkDPAAddrEn
(optional)
Input
Phase Alignment DPA Address Enable. Active
RDClkDiv_User high signal that enables the SnkDPARamAddr
counter.
SnkDPAClkDlyRst
(optional)
Output
Phase Alignment IDELAY Reset. Active high
signal used to reset the IDELAY inserted in the
RDClkDiv_User RDClk path of the external sink clocking module.
This option is only available when the “DPA Clock
Adjustment” feature is enabled.
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DS823 July 25, 2012
Product Specification