DS823 Datasheet, PDF (13/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 4: Sink AXI4-Lite Control Interface Signals (Cont’d)
Name
Direction Clock Domain
Description
Write Response Channel
AXI_SNK_BREADY
Input
AXI4-Lite Write Response User Handshake.
Indicates the user is ready to accept a write response.
AXI_SNK_ACLK When both BREADY and BVALID are asserted on a
rising edge of AXI_SNK_ACLK, one write response
transaction is read out of the core.
AXI_SNK_BVALID
Output
AXI4-Lite Write Response Core Handshake.
Indicates the core is presenting a valid write
response. When both BREADY and BVALID are
asserted on a rising edge of AXI_SNK_ACLK, one
AXI_SNK_ACLK write response transaction is read out of the core.
Each write transaction will generate a write response,
regardless of whether the write succeeded. The Error
Bus (below) provides further signaling in regards to
errors that occur during write operations.
Sideband Error Bus
SNK_BRESP_ERR[7:0]
Output
AXI4-Lite Error Bus. Each bit of this bus
corresponds to a specific AXI4-Lite Error condition.
The error conditions detected are reported as follows:
SNK_BRESP_ERR [0]: Write Response counter is
full. No further writes or reads will be processed until
at least one Write Response is read from the core
using BREADY/BVALID.
AXI_SNK_ACLK _{SNK_BRESP_ERR[1]: Write transaction to the}
Configuration space failed.
SNK_BRESP_ERR [2]: Write transaction to the
Calendar space has failed.
SNK_BRESP_ERR[3]:Read/Write has missed a valid
address
SNK_BRESP_ERR [4:7]: Reserved bits (tied low).
DS823 July 25, 2012
www.xilinx.com
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