DS823 Datasheet, PDF (7/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Sink Interfaces
The Sink core has four primary interfaces: the SPI-4.2 interface, the AXI4-Stream FIFO interface, the
AXI4-Lite Control interface, and the Control and Status interface.
Sink SPI-4.2 Interface
Table 1 contains the Sink SPI-4.2 interface signals.
Table 1: Sink SPI-4.2 Interface Signals
Name
Direction
Clock
Domain
Description
RDClk_P
RDClk_N
RDat_P[15:0]
RDat_N[15:0]
RCtl_P
RCtl_N
Input
Input
Input
n/a
RDClk
RDClk
SPI-4.2 Receive Data Clock (LVDS). Source-synchronous clock
received with RDat and RCtl. The rising and falling edges of this
clock (DDR) are used to clock RDat and RCtl.
SPI-4.2 Receive Data Bus (LVDS). The 16-bit data bus used to
receive SPI-4.2 data and control information.
SPI-4.2 Receive Control (LVDS). SPI-4.2 Interface signal that
indicates whether data or control information is present on the RDat
bus. When RCtl is deasserted, data is present on RDat. When RCtl
is asserted, control information is present on RDat.
RSClk_P
RSClk_N
Output
n/a SPI-4.2 Receive Status Clock (LVDS/LVTTL). Source-
synchronous clock transmitted with RStat at 1/4 or 1/8 rate of the
RDClk. The rate of the status clock is controlled by the static
configuration parameter RSClkDiv.
RStat_P[1:0]
RStat_N[1:0]
Output
RSClk SPI-4.2 Receive FIFO Status (LVDS/LVTTL). FlFO Status Channel
flow control interface.
Sink User Interface
The Sink user interface can be divided into the following subgroups, based on function.
• Control and status interface
• AXI4-Stream FIFO interface
• AXI4-Lite Control interface
DS823 July 25, 2012
www.xilinx.com
7
Product Specification