DS823 Datasheet, PDF (30/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
The source core reference clock (SysClk) must have less than 50 ps of jitter since any jitter present on
the SysClk input would appear on the TDClk output. Similarly, the duty cycle distortion on the
SysClk should also be minimized. For source cores that use MMCM to generate the internal clocks, the
SysClk duty cycle must be 45/55 or tighter. For SysClk cores that use regional clocking scheme to
generate the internal clocks, the SysClk duty cycle must be 48/52 or tighter. To reduce the jitter and
duty cycle distortion of the output TDClk, place the clocking and output component as close as
possible to each other. For more information, see the UG784, SPI-4.2 User Guide.
Table 13: Sink Core Clocking Option for Virtex-7 and Kintex-7 FPGAs
Clocking Option
BUFR
BUFG ⁽¹⁾
MMCM
Regional clocking
1
0/1
0
Global clocking
0
4/5
1
1. The Sink Core requires SnkIdelayRefClk to be driven by a global clock buffer. This reference clock provides a time reference to
IDELAYCTRL modules to calibrate all the individual delay elements (IDELAY) in the region. Multiple cores need only one global clock
buffer to distribute the SnkIdelayRefClk.
Table 14: Source Core SysClk Clocking Option for Virtex-7 and Kintex-7 FPGAs
Clocking Option
BUFR
BUFG
MMCM
Regional clocking
Global clocking⁽¹⁾
1
0
0
0
4
1
1. Global clocking is only supported for source cores that send data to Sink cores that are configured with Dynamic Phase Alignment.
Table 15: Source Core TSClk Clocking Option for Virtex-7 and Kintex-7 FPGAs
Clocking Option
BUFR
BUFG
Regional clocking
1
0
Global clocking
0
3
MMCM
0
1
The Global clocking option uses dedicated global (chip) routing. The Regional clocking option uses
clock region-specific resources.
The SPI-4.2 solution delivers the clocking circuitry external to the core. This allows a customized
clocking solution to be created based on individual system requirements. An example design is
provided to demonstrate the implementation of a clocking module for the core.
Multiple Core Instantiations
It is possible to implement multiple SPI-4.2 cores in a single target device. Larger Virtex-7 and Kintex-
7 devices can support more than four SPI-4.2 cores. See SPI-4.2 User Guide, for more details.
Verification
Extensive software testing with an internally developed verification platform is performed for each
SPI-4.2 release. Using the in-house verification environment, the SPI-4.2 core was tested in three stages:
• Functional (RTL) verification
• Gate-level (post ngdbuild back-annotated HDL) verification
• Gate-level with back-annotated Timing (with SDF file) verification targeting the following
device/frequency combinations:
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DS823 July 25, 2012
Product Specification