DS823 Datasheet, PDF (11/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 3: Sink AXI4-Stream FIFO Interface Signals (Cont’d)
Name
Direction
Description
SNKFF_ALMOSTFULL_N
Output
Sink FIFO Almost Full. When asserted (active low), this signal
indicates that the Sink core is approaching full (as defined by the
parameter SnkAFThresAssert), and that immediate action should
be taken to prevent overflow.
SNKFF_OVERFLOW_N
Output
Sink FIFO Overflow. When asserted (active low), this signal
indicates that the Sink core has overflowed and is in an error
condition. Data will be lost if SNKFF_OVERFLOW_N is asserted,
since no data is written into the FIFO when the overflow signal is
asserted.
Sink AXI4-Lite Control Interface
The Sink AXI4-Lite Control interface is used to program the calendar memory, status memory, and
static configuration memory. This memory space is defined in Figure 4
The calendar determines the status channel order and frequency. Through this interface, the user can
program the calendar buffer to determine the order and frequency with which channel status is sent on
the SPI-4.2 interface. The Status memory enables the user to send flow control data to the transmitting
device. Flow control may be automatically or manually implemented. The static configuration memory
enables customization of the core based on individual system requirements. These settings are
statically driven inside the core by writing to registers through the Control interface. Table 4 describes
the Control interface signals, and Table 5 defines the static configuration parameters.
Table 4: Sink AXI4-Lite Control Interface Signals
Name
Direction Clock Domain
Description
AXI_SNK_ACLK
Input
N/A
AXI4-Lite Clock. All Sink AXI4-Lite signals are
synchronous to the rising edge of this clock
AXI_SNK_ARESETN
Input
AXI4-Lite Reset. Active-low signal that enables the
user to reset the AXI4-Lite interface and all
associated logic and memories to chosen CORE
AXI_SNK_ACLK
Generator settings. The reset signal can be asserted
asynchronously, but deassertion must be
synchronous after the rising edge of ACLK. See the
AMBA AXI4 Protocol specification for more
information.
Read Address Channel
AXI_SNK_ARREADY
Output
AXI4-Lite Read Address Core Handshake.
Indicates the core is ready to accept a read address.
AXI_SNK_ACLK
When both ARREADY and ARVALID are asserted on
a clock cycle, a one-word read request occurs for the
address provided on ARADDR and the core fetches
the contents of that address.
AXI_SNK_ARVALID
Input
AXI4-Lite Read Address User Handshake.
Indicates the user is presenting a valid read address.
AXI_SNK_ACLK
When both ARREADY and ARVALID are asserted on
a clock cycle, a one-word read request occurs for the
address provided on ARADDR and the core fetches
the contents of that address
AXI_SNK_ARADDR[9:0]
Input
AXI_SNK_ACLK
AXI4-Lite Read Address. Address to be read by the
user application.
DS823 July 25, 2012
www.xilinx.com
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Product Specification