DS823 Datasheet, PDF (23/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 9: Source AXI4-Lite Control interface Signals (Cont’d)
Name
Direction Clock Domain
Description
Read Data Channel
AXI_SRC_RREADY
Input
AXI4-Lite Read Data User Handshake. Indicates the
user is ready to accept read data. When both
AXI_SRC_ACLK
RREADY and RVALID are asserted on a clock cycle,
one data beat is read out of the core. This handshake
completes the transaction begun by the
ARREADY/ARVALID handshake.
AXI_SRC_RVALID
Output
AXI4-Lite Read Data Core Handshake. Indicates the
core is presenting valid read data. When both
AXI_SRC_ACLK
RREADY and RVALID are asserted on a clock cycle,
one data beat is read out of the core. This handshake
completes the transaction begun by the
ARREADY/ARVALID handshake.
AXI_SRC_RDATA[31:0]
Output
AXI4-Lite Read Data. Data read from address
AXI_SRC_ACLK location provided on ARADDR is presented here. Bit
0 is the LSB.
Write Address Channel
AXI_SRC_AWREADY
Output
AXI4-Lite Write Address Core Handshake.
Indicates the core is ready to accept a write address.
When both AWREADY and AWVALID are asserted on
AXI_SRC_ACLK a clock cycle, one write address beat is accepted by
the core. Once both the WREADY/WVALID and
AWREADY/AWVALID handshakes occur
independently, one write transaction is complete.
AXI_SRC_AWVALID
Input
AXI4-Lite Write Address User Handshake.
Indicates the user is presenting a valid write address.
When both AWREADY and AWVALID are asserted on
AXI_SRC_ACLK a clock cycle, one write address beat is accepted by
the core. Once both the WREADY/WVALID and
AWREADY/AWVALID handshakes occur
independently, one write transaction is complete.
AXI_SRC_AWADDR[9:0]
Input
AXI_SRC_ACLK
AXI4-Lite Write Address. Address to be written by
the user application.
Write Data Channel
AXI_SRC_WREADY
Output
AXI4-Lite Write Data Core Handshake. Indicates the
core is ready to accept write data and strobe. When
both WREADY and WVALID are asserted on a clock
AXI_SRC_ACLK cycle, one write address beat is accepted by the core.
Once both the WREADY/WVALID and
AWREADY/AWVALID handshakes occur
independently, one write transaction is complete
AXI_SRC_WVALID
Input
AXI4-Lite Write Data User Handshake. Indicates the
user is presenting valid write data and strobe. When
both WREADY and WVALID are asserted on a clock
AXI_SRC_ACLK cycle, one write address beat is accepted by the core.
Once both the WREADY/WVALID and
AWREADY/AWVALID handshakes occur
independently, one write transaction is complete.
AXI_SRC_WDATA[31:0]
Input
AXI_SRC_ACLK
AXI4-Lite Write Data. Data written into the core. Bit 0
is the LSB.
AXI_SRC_WSTRB[3:0]
Input
AXI4-Lite Write Strobe. Byte enable associated with
AXI_SRC_ACLK
AXI_SRC_WDATA. Bit 0 enables WDATA[7:0], bit 1
enables WDATA[15:8], bit 2 enables WDATA[23:16],
and bit 3 enables WDATA[32:24].
DS823 July 25, 2012
www.xilinx.com
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Product Specification