DS823 Datasheet, PDF (3/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Functional Overview
The SPI-4.2 solution consists of two separate modules: the Sink core and the Source core. The Sink core
receives data and sends status on its SPI-4.2 interface; the Source core transmits data and receives status
on its SPI-4.2 interface.
Sink Core
The Sink core receives 16-bit source synchronous data on the SPI-4.2 interface and combines these bits
into 64-bit or 128-bit data words on the AXI4-Stream FIFO interface. The core also processes 2-bit status
information (for each channel) from the AXI4-Lite Control interface and transmits it in sequence on the
SPI-4.2 interface with the appropriate framing and DIP2 information. In addition to data, other signals
associated with the operational state of the core and received packets are also available. These signals
include FIFO status and SPI-4.2 protocol violations.
The Sink core has four primary interfaces: the SPI-4.2 interface, the AXI4-Stream FIFO interface, the
AXI4-Lite Control interface, and the Control and Status interface.
DS823 July 25, 2012
www.xilinx.com
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Product Specification