DS823 Datasheet, PDF (6/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
X-Ref Target - Figure 3
Source
Control
and Status
Interface
Source
User
Clocking
Interface
Source
AXI4-Stream
FIFO
Interface
Reset_n
SrcTriStateEn
SrcEn
SrcOof
SrcDIP2Err
SrcPatternErr
IdleRequest
TrainingRequest
SysClkDiv _User
SysClk0_User
S_AXIS_SRCFF_ACLK
S_AXIS_SRCFF_ARESETN
S_AXIS_SRCFF_TVALID
S_AXIS_SRCFF_TID[7:0]
S_AXIS_SRCFF_TDATA[63:0] or [127:0]
S_AXIS_SRCFF_TKEEP[7:0] or [15:0]
S_AXIS_SRCFF_SOP
S_AXIS_SRCFF_TLAST
S_AXIS_SRCFF_ERR
S_AXIS_SRCFF_TREADY
AXI SPI-4.2 Source Core
Source
Data FIFO
Source
Data Transmit
Source
AXI 4-Stream
Status
Interface
M_AXIS_SRCSTAT_ACLK
**M_AXIS_SRCSTAT_TUSER[1:0]
M_AXIS_SRCSTAT_TVALID
M_AXIS_SRCSTAT_TID[7:0]
Source
AXI4-Lite
Control
Interface
AXI _SRC_ACLK
AXI _SRC_ARESETN
SRC_BRESP_ERR[7:0]
AXI _SRC_ARREADY
AXI _SRC_ARVALID
AXI _SRC_ARADDR[9:0]
AXI _SRC_RREADY
AXI _SRC_RVALID
AXI _SRC_RDATA[31:0]
AXI _SRC_AWREADY
AXI _SRC_AWVALID
AXI _SRC_AWADDR[9:0]
AXI _SRC_WREADY
AXI _SRC_WVALID
AXI _SRC_WDATA[31:0]
AXI _SRC_WSTRB[3:0]
AXI _SRC_BREADY
AXI _SRC_BVALID
Source
Status Logic
Source
AXI4-Lite
Memory Space
Source
Status Receive
TDClk
TDat[15:0]
TCtl
TSClk
TStat[1:0]
Source
SPI4.2
Interface
Figure 3: Source Core Block Diagram and I/O Interface Signals
Core Interfaces
This section provides definitions of the interface signals for the Sink and Source cores.
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DS823 July 25, 2012
Product Specification