DS823 Datasheet, PDF (10/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 3: Sink AXI4-Stream FIFO Interface Signals (Cont’d)
Name
Direction
Description
M_AXIS_SNKFF_TVALID
Output
Sink FIFO Data Valid Handshake. Indicates the core is
presenting valid streaming data. When both TREADY and
TVALID are asserted on the rising edge of
M_AXIS_SNKFF_ACLK, one data beat is transferred. When
asserted (active high), this signal indicates that the information on
M_AXIS_SNKFF_TDATA, M_AXIS_SNKFF_TID,
M_AXIS_SNKFF_SOP, M_AXIS_SNKFF_TLAST,
M_AXIS_SNKFF_BURSTERR, M_AXIS_SNKFF_TKEEP,
M_AXIS_SNKFF_ERR, M_AXIS_SNKFF_DIP4ERR,
M_AXIS_SNKFF_PAYLOADERR, and
M_AXIS_SNKFF_PAYLOADDIP4 are valid.
M_AXIS_SNKFF_TID[7:0]
Output
Sink FIFO Channel Address. Channel number associated with
the data on M_AXIS_SNKFF_TDATA.
M_AXIS_SNKFF_TDATA[63:0]
or
M_AXIS_SNKFF_TDATA[127:0]
Output
Sink FIFO Data Out. The Sink FIFO data bus. Bit 0 is the LSB.
The core can be configured to have a 64-bit or 128-bit Interface.
The 128-bit interface enables the user to run at half the clock rate
required for a 64-bit interface.
M_AXIS_SNKFF_TKEEP[7:0]
or
M_AXIS_SNKFF_TKEEP[15:0]
Output
Sink FIFO Data Strobe. This signal indicates which bytes on the
M_AXIS_SNKFF_TDATA bus are valid when the
M_AXIS_SNKFF_TLAST signal is asserted (i.e. byte enable).
M_AXIS_SNKFF_TKEEP[7:0] is used with a 64-bit interface.
M_AXIS_SNKFF_TKEEP[15:0] is used with a 128-bit interface.
M_AXIS_SNKFF_SOP
Output
Sink FIFO Start of Packet. When asserted (active high), this
signal indicates the start of a packet is being read out of the Sink
FIFO.
M_AXIS_SNKFF_TLAST
Output
Sink FIFO End of Packet (EOP). When asserted (active high),
this signal indicates that the end of a packet is being read out of
the Sink FIFO.
M_AXIS_SNKFF_ERR
Output
Sink FIFO Error. When asserted (active high), this signal
indicates that the current packet is terminated with an EOP abort
condition. This signal is only asserted when
M_AXIS_SNKFF_TLAST is asserted.
M_AXIS_SNKFF_DIP4ERR
Output
Sink FIFO DIP-4 Error. When asserted (active high), this signal
indicates that a DIP-4 parity error was detected with the SPI-4.2
control word ending a packet or burst of data. This signal is
asserted at the end of that packet or burst of data.
M_AXIS_SNKFF_PAYLOADDIP4
Output
Sink FIFO Payload DIP4 Error. When asserted (active high), this
signal indicates that a DIP-4 parity error was detected with the
SPI-4.2 control word starting a packet or burst of data. This signal
is asserted at the end of that packet or burst of data.
M_AXIS_SNKFF_BURSTERR
Output
Sink FIFO Burst Error. When asserted (active high), this signal
indicates that the Sink core has received data that was terminated
on a non-credit boundary without an EOP.
M_AXIS_SNKFF_BURSTERR may be used by the user’s logic to
indicate missing EOPs, or incorrectly terminated bursts. In this
case the Sink core does not assert M_AXIS_SNKFF_TLAST or
M_AXIS_SNKFF_ERR.
M_AXIS_SNKFF_PAYLOADERR
Output
Sink FIFO Payload Error. When asserted (active high), this
signal indicates that the received data was not preceded by a
valid payload control word. Since it is not clear what the packet
Address and SOP should be, it is flagged as an error. This is
asserted with each data word coming out of the FIFO, and will
remain asserted until a valid payload control word is followed by
data.
10
www.xilinx.com
DS823 July 25, 2012
Product Specification