DS823 Datasheet, PDF (27/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 11: Source Static Configuration Parameter Definition (Cont’d)
Name
Range
Description
SrcBurstLen[9:0]
If SrcBurstMode = 1, 1-1023
If SrcBurstMode = 0, 1- 256
Values equal to 0 gets set to 1.
Source Burst Length. The Source core
automatically segments packets larger than this
parameter into multiple bursts, which are each
SrcBurstLen in length. This parameter is defined in
credits (16 bytes).
SrcBurstMode
0 or 1
Source Burst Mode. When set to zero, the Source
core transmits data in the FIFO if the data is
terminated by an EOP or if there is a complete credit
of data.
When set to1, the Source core only transmits data
that is terminated by an EOP or when there is data
in the FIFO equal to the maximum burst length
defined by SrcBurstLen, or when the channel
address changes.
Sink Data Capture Implementation
The SPI-4.2 core uses SelectIO™ technology to implement dynamic-phase alignment (DPA) and static-
phase alignment as defined by the SPI-4.2 OIF specification. Virtex-7 and Kintex-7 FPGAs include
ChipSync technology to enhance I/O capability when used in source-synchronous applications like
SPI-4.2.
The SPI-4.2 DPA solution leverages ChipSync technology to perform data-eye detection and word
alignment. Using this dedicated hardware reduces the FPGA slice resources required for DPA (~50%)
and provides precision data sampling. Additionally, the ChipSync capability is supported in every I/O
pin, enabling full flexibility in selecting the pin-out for the SPI-4.2 interface. The SPI-4.2 DPA solution is
available for Virtex-7 and Kintex-7 FPGAs.
Virtex-7 and Kintex-7 FPGAs provide an abundance of clock resources for implementing multiple SPI-
4.2 cores in a single device. These clock resources are available for both dynamic and static alignment,
enabling the user to select the clocking scheme best suited to their design. The user interface and I/O
pinout of the core remain the same, regardless of the type of alignment implemented.
IDELAYCTRL Module
The SPI-4.2 core uses ChipSync IDELAY function in Virtex-7 and Kintex-7 FPGAs to perform data-eye
detection. The IDELAYCTRL module continuously calibrates the IDELAY elements in its region to
reduce the effects of process, voltage, and temperature variations. The IDELAYCTRL modules exist in
every I/O column in every clock region. The IDELAYCTRL modules must be instantiated in the user
design. See the SPI-4.2 User Guide for more information.
Dynamic Alignment
The Sink core can be configured to support dynamic-phase alignment (DPA) on the incoming source
synchronous SPI-4.2 data stream (RCtl and RDat[15:0] with respect to the RDClk). DPA provides
increased system timing margin on the SPI-4.2 interface by removing data skew across the ingress SPI-
4.2 bus as part of an interface timing budget. Because of this, it is the recommended alignment solution.
In Virtex-7 and Kintex-7 devices, DPA dynamic alignment is a two-phase process. First, the
implementation determines the ideal sampling point for each incoming bit, independent of the timing
of any other bit, by using the IDELAY/ISERDES functions of the ChipSync. The second phase uses the
DS823 July 25, 2012
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Product Specification