DS823 Datasheet, PDF (8/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Sink Control and Status Interface
The Sink core control and status interface signals control the operation of the Sink core and provide
status information that is not associated with a specific channel (port) or packet. Table 2 defines these
Sink control and status interface signals. The interface also provides information regarding the status
and debug of Dynamic Phase Alignment (DPA), if the DPA option is selected. These DPA status and
debug signals are described in Dynamic Alignment.
Table 2: Sink Control and Status Interface Signals
Name
Direction Clock Domain
Description
Reset_n
Input
Reset. Active low signal that asynchronously initializes
internal flip-flops, registers, and counters. When Reset_n is
asserted, the Sink core will go out of frame and the entire
data path is cleared (including the FIFO). The Sink core will
n/a
also assert SnkOof, and deassert SnkBusErr and
SnkTrainValid. When Reset_n is asserted, the Sink core will
transmit framing "11" on RStat and continue to drive RSClk.
Following the deassertion of Reset_n, the Sink calendar
should be programmed if the calendar is initialized in-circuit.
SnkEn
Input
Sink Enable. Active high signal that enables the Sink core.
When SnkEn is deasserted, the Sink core will go out of frame
and will not store any additional data in the FIFO. The current
contents of the FIFO remain intact.
RDClkDiv_User _{The Sink core will also assert SnkOof, and deassert}
SnkBusErr and SnkTrainValid. When SnkEn is deasserted,
the Sink core will transmit framing "11" on RStat and continue
to drive RSClk.
SnkIdelayCtlRdy
Input
IDELAYCTRL Ready. Active high signal that indicates when
the IDELAY modules are calibrated. The IDELAYCTRLs must
be instantiated in the wrapper by the user to calibrate the
RDClkDiv_User IDELAYs connected to RDat[15:0], RCtl, RDClk. Additionally,
all the ready signals from these IDELAYCTRLs must be
ANDed together to provide the signal that connects the
SnkIdelayCtlRdy signal.
SnkOof
Output
Sink Out-of-Frame. Active high signal indicating that the
SPI-4.2 Sink block is not in frame. This signal is asserted
RDClkDiv_User
when SnkEn is deasserted or the Sink block loses
synchronization with the data received on the SPI-4.2
Interface. This signal is deasserted once the Sink block
reacquires synchronization with the received SPI-4.2 data.
SnkBusErr
Output
Sink Bus Error. Active high signal that indicates SPI-4.2
protocol violations or bus errors that are not associated with
RDClkDiv_User a particular packet. Information on the specific error condition
that caused the SnkBusErr assertion is provided on
SnkBusErrStat.
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DS823 July 25, 2012
Product Specification