DS823 Datasheet, PDF (17/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Source Interfaces
The Source core has five primary interfaces: the SPI-4.2 interface, the AXI4-Stream FIFO interface, the
AXI4-Stream Status interface, the AXI4-Lite Control interface, and the Control and Status interface.
Source SPI-4.2 Interface
Table 6 defines the signals on the Source SPI-4.2 interface.
Table 6: Source SPI-4.2 Interface Signals
Name
Direction
Clock
Domain
Description
TDClk_P
TDClk_N
TDat_P[15:0]
TDat_N[15:0]
TCtl_P
TCtl_N
TSClk_P
TSClk_N
TStat_P[1:0]
TStat_N[1:0]
Output
Output
Output
Input
Input
n/a
TDClk
TDClk
n/a
TSClk
SPI-4.2 Transmit Data Clock (LVDS). Source synchronous clock
transmitted with TDat. The rising and falling edges of this clock
(DDR) are used to clock TDat and TCtl.
SPI-4.2 Transmit Data Bus (LVDS). The 16-bit data bus is used
to transmit SPI-4.2 data and control information.
SPI-4.2 Transmit Control (LVDS). SPI-4.2 Interface signal that
defines whether data or control information is present on the TDat
bus. When TCtl is Low, data is present on TDat. When TCtl is High,
control information is present on TDat.
SPI-4.2 Transmit Status Clock (LVDS/LVTTL). Source
synchronous clock that is received by the Source core with TStat
at 1/4 rate (or 1/8 rate) of TDClk.
SPI-4.2 Transmit FIFO Status (LVDS/LVTTL). FlFO-Status-
Channel flow control interface.
Source User Interface
The Source user interface can be divided into the following subgroups, based on function:
• Control and status interface
• AXI4-Stream FIFO interface
• AXI4-Lite Control interface
• AXI4-Stream Status Interface
DS823 July 25, 2012
www.xilinx.com
17
Product Specification