DS823 Datasheet, PDF (24/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 9: Source AXI4-Lite Control interface Signals (Cont’d)
Name
Direction Clock Domain
Description
Write Response Channel
AXI_SRC_BREADY
Input
AXI4-Lite Write Response User Handshake.
Indicates the user is ready to accept a write response.
AXI_SRC_ACLK When both BREADY and BVALID are asserted on a
rising edge of AXI_SRC_ACLK, one write response
transaction is read out of the core.
AXI_SRC_BVALID
Output
AXI4-Lite Write Response Core Handshake.
Indicates the core is presenting a valid write response.
When both BREADY and BVALID are asserted on a
rising edge of AXI_SRC_ACLK, one write response
AXI_SRC_ACLK transaction is read out of the core. Each write
transaction will generate a write response, regardless
of whether the write succeeded. The Error Bus
(below) provides further signaling in regards to errors
that occur during write operations.
Sideband Error Bus
SRC_BRESP_ERR[7:0]
Output
AXI4-Lite Error Bus. Each bit of this bus corresponds
to a specific AXI4-Lite Error condition. The error
conditions detected are reported as follows:
• SRC_BRESP_ERR [0]: Write Response counter is
full. No further writes or reads will be processed
until at least one Write Response is read from the
core using BREADY/BVALID.
• SRC_BRESP_ERR[1]: Write transaction to the
AXI_SRC_ACLK _{Configuration space failed.}
• SRC_BRESP_ERR [2]: Write transaction to the
Calendar space has failed.
• SRC_BRESP_ERR[3]: Write transaction to the
Status space has failed.
• SRC_BRESP_ERR[4]:Read/Write transaction has
missed a valid address.
• SRC_BRESP_ERR [5:7]: Reserved bits (tied low).
Source AXI4-Stream Status Interface
The Source AXI4-Stream interface provides flow control information about the SPI-4.2 link.
When the core is used in Addressable Status mode, the interface provides the channel number for the
most recently updated SPI-4.2 channel status on M_AXIS_SRCSTAT_TID, qualified by the
M_AXIS_SRCSTAT_TVALID signal. The channel status itself must be accessed via the AXI4-Lite
Control interface, with each read providing status for four channels.
When the core is used in Transparent Status mode, the M_AXIS_SRCSTAT_TUSER[1:0] bus is added.
This port provides the SPI-4.2 status as received on TStat with minimal latency. In this mode, the
M_AXIS_SRCSTAT_TID bus indicates the channel to which the current status shown on
M_AXIS_SRCSTAT_TUSER belongs. Both M_AXIS_SRCSTAT_TID and M_AXIS_SRCSTAT_TUSER
are qualified by M_AXIS_SRCSTAT_TVALID.
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DS823 July 25, 2012
Product Specification