DS823 Datasheet, PDF (32/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Performance in Kintex-7 FPGAs (Preliminary)
Table 18 contains the performance numbers for the SPI-4.2 cores that target Kintex-7 devices.
Table 18: Performance in Kintex-7 Devices
Alignment Type
Speed Grade
Performance⁽¹⁾
Static
-1, -2, -3
622 Mbps-700 Mbps
Dynamic
-1
622 Mbps-900 Mbps
Dynamic
-2
622 Mbps-900 Mbps
Dynamic
-3
622 Mbps-1 Gbps
1. Performance numbers shown use Kintex-7 FPGA High Performance (HP) I/O. Use of High Range (HR) I/O
is supported but may limit upper bound of performance range. See DS182, Kintex-7 FPGAs Data Sheet: DC
and Switching Characteristics for supported performance ranges using HR I/O. Between this document and
DS182, the SPI-4.2 core is limited to the smaller of the two performance numbers.
References
1. PMC-Sierra, Inc., POS-PHY Level-4, A Saturn Packet and Cell Interface Specification for OC-192
SONET/SDH and 10 Gb/s Ethernet Applications, Issue 5: June 2000.
2. Optical Internetworking Forum (OIF), OIF-SPI4-02.1 System Packet Interface Level-4 (SPI-4) Phase 2
Revision 1: OC-192 System Interface for Physical and Link Layer Devices.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided under the terms of the Xilinx Core License Agreement.
The module is shipped as part of the Vivado Design Suite. For full access to all core functions in
simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales
representative for information about pricing and availability.
For more information, visit the SPI-4.2 product page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property
page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools,
contact your local Xilinx sales representative.
Revision History
The following table shows the revision history for this document:
Date
3/1/11
6/22/11
Version
1.0
2.0
Description of Revisions
Initial Xilinx release.
Updated core to v11.2 and ISE Design Suite to v13.2.
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DS823 July 25, 2012
Product Specification