DS823 Datasheet, PDF (5/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Source Core
The Source core transmits 16-bit source synchronous data on its SPI-4.2 interface by processing and
formatting 64-bit or 128-bit data words from the AXI4-Stream FIFO interface. The core also processes 2-
bit status (for each channel) received on the SPI-4.2 interface and provides them on the AXI4-Lite
Control interface (or the AXI4-Stream Status interface for Transparent mode). In addition to data, other
signals associated with operational state and transmitted packets are also available. These signals
include FIFO status and SPI-4.2 protocol violations.
The Source core has five primary interfaces: the SPI-4.2 interface, the AXI4-Stream FIFO interface, the
AXI4-Stream Status interface, the AXI4-Lite Control interface, and the Control and Status interface.
Figure 3 shows input and output signals and functional blocks of the Source core. The interface signals
to each of the functional modules are described in Core Interfaces, page 6.
DS823 July 25, 2012
www.xilinx.com
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Product Specification