DS823 Datasheet, PDF (21/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 8: Sink AXI4-Stream FIFO Interface Signals (Cont’d)
Name
Direction
Clock Domain
Description
S_AXIS_SRCFF_TKEEP[15:0]
or
S_AXIS_SRCFF_TKEEP[7:0]
Input
Source FIFO Strobe. This signal
indicates which bytes on the
S_AXIS_SRCFF_TDATA bus are valid
when the S_AXIS_SRCFF_TLAST signal
is asserted (i.e. byte enable). When
S_AXIS_SRCFF_TLAST is deasserted,
S_AXIS_SRCFF_ACLK _{S_AXIS_SRCFF_TKEEP should always}
be set to all ones.
S_AXIS_SRCFF_TKEEP[7:0] is used
with a 64-bit interface.
S_AXIS_SRCFF_TKEEP[15:0] is used
with a 128-bit interface.
S_AXIS_SRCFF_SOP
Input
Source FIFO Start of Packet. When
S_AXIS_SRCFF_ACLK
asserted (active high), indicates that the
start of a packet is being written into the
Source FIFO.
S_AXIS_SRCFF_TLAST
Input
Source FIFO End of Packet. When
asserted (active high), indicates that the
S_AXIS_SRCFF_ACLK end of a packet is being written into the
Source FIFO. May be concurrent with
S_AXIS_SRCFF_SOP.
S_AXIS_SRCFF_ERR
Input
Source FIFO Error. When asserted
(active high) simultaneously with the
S_AXIS_SRCFF_TLAST flag, the current
packet written into the FIFO contains an
error. This causes an EOP abort to be
sent on the SPI-4.2 Interface.
S_AXIS_SRCFF_ERR can be used in
combination with
S_AXIS_SRCFF_ACLK
S_AXIS_SRCFF_TLAST to insert
erroneous DIP-4 values for testing
purposes. When S_AXIS_SRCFF_ERR
is asserted and S_AXIS_SRCFF_TLAST
is not asserted, the core inserts an EOP
(1 or 2 bytes depending on the
S_AXIS_SRCFF_TKEEP value) with an
erroneous DIP-4 value. The erroneous
DIP4 value is an inversion of the correctly
calculated value.
DS823 July 25, 2012
www.xilinx.com
21
Product Specification