DS823 Datasheet, PDF (18/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Source Control and Status Interface
The Source core control and status interface signals control the operation of the Source core and provide
status information that is not associated with a particular channel (port) or packet. Table 7 defines
Source control and status signals.
Table 7: Source Control and Status Signals
Name
Direction
Clock Domain
Description
Reset_n
Input
Reset_n. This active low, asynchronous control
signal enables the user to restart the entire Source
core, and causes the core to go out-of-frame. While
Reset_n is asserted, the Source core transmits idles
n/a
cycles on TDat. Coming out of Reset_n, the Source
core transmits training patterns.
Following the release of Reset_n, the Source
Calendar should be programmed if the calendar is to
be initialized in-circuit.
SrcEn
Input
SysClkDiv_User
Source Enable. Active high signal that enables the
Source core. When SrcEn is deasserted, the Source
core will not store or verify received status
information. The Source core will also assert SrcOof,
and deassert SrcDIP2Err, SrcPatternErr and
SrcStatFrameErr. When SrcEn is deasserted, the
Source core will transmit training patterns on TDat.
SrcOof
Output
SysClkDiv_User
Source Out-of-Frame. When this signal is asserted
(active high), it indicates that the SPI-4.2 Source
block is not in frame. This signal is asserted when the
Source block has lost synchronization on the transmit
FIFO status interface. This is caused by the receipt of
consecutive DIP-2 parity errors (determined by the
parameter NumDip2Errors), invalid received status
frame sequence (of four consecutive frame words
"11"), or when SrcEn is deasserted
This signal is deasserted once the Source block
reacquires synchronization with the SPI-4.2 transmit
Status Channel. Synchronization occurs when
consecutive valid DIP2 words (determined by the
Static Configuration parameter NumDip2Matches)
are received and SrcEn is asserted.
SrcDIP2Err
Output
Source DIP-2 Parity Error. When this signal is
asserted (active high), it indicates that a DIP-2 parity
M_AXIS_SRCSTAT_ACLK error was detected on TStat. This signal is asserted
for one clock cycle each time a parity error is
detected.
SrcStatFrameErr
Output
Source Status Frame Error: When this signal is
asserted (active high), it indicates that a non "11"
M_AXIS_SRCSTAT_ACLK frame word was received after DIP-2 on TStat. This
signal is asserted for one clock cycle each time a
frame word error is detected.
SrcPatternErr
Output
S_AXIS_SRCFF_ACLK
Source Data Pattern Error. When asserted (active
high), indicates that the data pattern written into the
Source FIFO is illegal. Illegal patterns include the
following:
• Burst of data terminating on a non-credit boundary
(not a multiple of 16 bytes) with no EOP.
• All S_AXIS_SRCFF_TKEEP not set to one when
S_AXIS_SRCFF_TLAST is deasserted.
This signal is asserted for one clock cycle each time
an illegal data pattern is written into the Source FIFO.
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DS823 July 25, 2012
Product Specification