DS823 Datasheet, PDF (19/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 7: Source Control and Status Signals (Cont’d)
Name
Direction
Clock Domain
Description
IdleRequest
Input
SysClkDiv_User
Idle Request.Active high signal that requests idle
control words be sent out of the Source SPI-4.2
interface. The Source core responds by sending out
idle control words at the next burst boundary. This
signal overrides normal SPI-4.2 data transfer
requests, but does not override training sequence
requests (TrainingRequest).
Activating the request for idle cycles does not affect
the Source FIFO contents or the user side operation.
TrainingRequest Input
SysClkDiv_User
Training Pattern Request. Active high signal that
requests training patterns be sent out of the Source
SPI-4.2 interface. The Source core responds by
sending out training patterns at the next burst
boundary. This signal overrides idle requests
(IdleRequest) and normal SPI-4.2 data transfers.
Activating the request for training cycles does not
affect the Source FIFO contents or the user side
operation.
SrcTriStateEn
Input
SysClkDiv_User
SrcTriStateEn. Active high control signal that
enables the user to tri-state the IOB drivers for the
following Source core outputs: TDClk, TDat[15:0],
and TCtl.
When SrcTriStateEn=0, the outputs are not tri-stated.
When SrcTriStateEn=1, the outputs are tri-stated.
Default setting for this signal is disabled
(SrcTriStateEn=0.)
SrcOofOverride Input
SysClkDiv_User
Source Out-of-Frame Override. When this signal is
asserted, the Source core behaves as if in-frame, and
sends data on TDat regardless of the status received
on TStat. This signal is used for system testing and
debugging.
DS823 July 25, 2012
www.xilinx.com
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Product Specification