DS823 Datasheet, PDF (25/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 10: Source AXI4-Stream Status Interface Signals
Name
Direction
Clock
Domain
Description
M_AXIS_SRCSTAT_ACLK
Input
N/A
Status Clock. All status AXI4-Stream signals are
synchronous to the rising edge of this clock.
M_AXIS_SRCSTAT_TID[7:0]
Output
M_AXIS_
SRCSTAT_
ACLK
Status Channel. The Source Status Channel is
an 8-bit bus containing the channel address that
is being updated on M_AXIS_SRCSTAT_TUSER
on the current clock cycle.
M_AXIS_SRCSTAT_TVALID
Output
M_AXIS_
SRCSTAT_
ACLK
Status Valid. When asserted indicates that
M_AXIS_SRCSTAT_TUSER and
M_AXIS_SRCSTAT_TID are valid.
When the core is processing DIP-2 or frame
words, TVALID is deasserted. A transition of
TVALID from 0 to 1 indicates that the core has
started a new calendar sequence.
M_AXIS_SRCSTAT_TUSER[1:0] Output
M_AXIS_ Status (Only Available in Transparent Mode).
SRCSTAT_ Represents the current status received on the
ACLK
SPI-4.2 TStat bus.
X-Ref Target - Figure 5
31
0x000
0x004
0x1F8
0x1FC
Calendar 3
... ^{Calendar 7}
Calendar 507
Calendar 511
23
Calendar 2
... ^{Calendar 6}
Calendar 506
Calendar 510
15
Calendar 1
... ^{Calendar 5}
Calendar 505
Calendar 509
7
0
Calendar 0
... ^{Calendar 4}
Calendar 504
Calendar 508
31
0x200
0x204
0x2F8
0x2FC
R
R _...
R
R
23
Ch3
Ch7
Ch251
Ch255
R
R _...
R
R
15
Ch2
Ch6
Ch250
Ch254
R
R _...
R
R
7
Ch1
Ch5
Ch249
Ch253
R
R _...
R
R
0
Ch0
Ch4
Ch254
Ch252
31
0x300
0x304
0x308
0x30C
0x310
23
15
R
NumDip2Matches[3:0]
R
SrcCalendar_Len[8:0]
R
SrcAFThresAssert[8:0]
R
AlphaData[7:0]
R
R
R
R
7
R
0
NumDip2Errors[3:0]
SrcCalendarM[7:0]
SrcAFThresNegate[8:0]
DataMaxT[15:0]
SrcBurstLen[9:0]
SrcBurstMode
Figure 5: Source AXI4-Lite Memory Space
DS823 July 25, 2012
www.xilinx.com
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Product Specification